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Paper Abstract and Keywords
Presentation 2023-03-02 16:50
Reducing Conflict Misses with Multiple Indexings in Compressed Caches
Tasuku Fukami, Shinya Takamaeda (UTokyo) VLD2022-98 HWS2022-69
Abstract (in Japanese) (See Japanese page) 
(in English) Cache memory is a common hardware mechanism that improves memory access performance. To enlarge cache capacity virtually, various cache compression techniques have been studied. A drawback of cache compression is that it inevitably causes an increase in tag stores. Thus, the ``superblock'' method has been proposed to minimize the tag area overhead. However, the superblock structure can have a negative impact on the cache performance.
In this paper, we propose a compressed cache mechanism that mitigates super-block's downside. The proposed mechanism achieved up to $times 1.14$ higher hit rate from the baseline and execution time improvement of up to $3.3,%$.
Keyword (in Japanese) (See Japanese page) 
(in English) Cache Memory / Compressed Cache / Conflict Miss / Indexing / / / /  
Reference Info. IEICE Tech. Rep., vol. 122, no. 402, VLD2022-98, pp. 131-136, March 2023.
Paper # VLD2022-98 
Date of Issue 2023-02-22 (VLD, HWS) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2022-98 HWS2022-69

Conference Information
Committee HWS VLD  
Conference Date 2023-03-01 - 2023-03-04 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
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Paper Information
Registration To VLD 
Conference Code 2023-03-HWS-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Reducing Conflict Misses with Multiple Indexings in Compressed Caches 
Sub Title (in English)  
Keyword(1) Cache Memory  
Keyword(2) Compressed Cache  
Keyword(3) Conflict Miss  
Keyword(4) Indexing  
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1st Author's Name Tasuku Fukami  
1st Author's Affiliation The University of Tokyo (UTokyo)
2nd Author's Name Shinya Takamaeda  
2nd Author's Affiliation The University of Tokyo (UTokyo)
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Speaker Author-1 
Date Time 2023-03-02 16:50:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2022-98, HWS2022-69 
Volume (vol) vol.122 
Number (no) no.402(VLD), no.403(HWS) 
Page pp.131-136 
#Pages 6 
Date of Issue 2023-02-22 (VLD, HWS) 

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