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| Paper Abstract and Keywords | ||
| Presentation | 2023-03-03 09:55 Track Assignment considering Routing Crossing Relations to Improve Feasibility in Bottleneck Channel Routing Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Molongo Mathieu, Makoto Minami, Katsuya Nishioka (Jedat)  VLD2022-101 HWS2022-72 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Design automation that realizes analog integrated circuits to meet performance specifications in a small area is desired. The proposed algorithm generates feasible solutions in cases that the conventional algorithm generates infeasible solutions in addition to cases that the conventional algorithm generates feasible solutions, by determining track assignments for each net cluster defined by the routing crossing relations in “Bottleneck Channel Routing” in which two wires go through a routing track in bottleneck region to reduce the layout area. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | 2-layer Bottleneck Routing / Analog VLSI / / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 122, no. 402, VLD2022-101, pp. 149-154, March 2023. | |
| Paper # | VLD2022-101 | |
| Date of Issue | 2023-02-22 (VLD, HWS) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2022-101 HWS2022-72 |
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| Conference Information | |
| Committee | HWS VLD |
| Conference Date | 2023-03-01 - 2023-03-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2023-03-HWS-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Track Assignment considering Routing Crossing Relations to Improve Feasibility in Bottleneck Channel Routing |
| Sub Title (in English) | |
| Keyword(1) | 2-layer Bottleneck Routing |
| Keyword(2) | Analog VLSI |
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| 1st Author's Name | Kazuya Taniguchi |
| 1st Author's Affiliation | Tokyo Institute of Technology (Tokyo Tech) |
| 2nd Author's Name | Satoshi Tayu |
| 2nd Author's Affiliation | Tokyo Institute of Technology (Tokyo Tech) |
| 3rd Author's Name | Atsushi Takahashi |
| 3rd Author's Affiliation | Tokyo Institute of Technology (Tokyo Tech) |
| 4th Author's Name | Molongo Mathieu |
| 4th Author's Affiliation | Jedat (Jedat) |
| 5th Author's Name | Makoto Minami |
| 5th Author's Affiliation | Jedat (Jedat) |
| 6th Author's Name | Katsuya Nishioka |
| 6th Author's Affiliation | Jedat (Jedat) |
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| Speaker | Author-1 |
| Date Time | 2023-03-03 09:55:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2022-101, HWS2022-72 |
| Volume (vol) | vol.122 |
| Number (no) | no.402(VLD), no.403(HWS) |
| Page | pp.149-154 |
| #Pages | 6 |
| Date of Issue | 2023-02-22 (VLD, HWS) |
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