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Paper Abstract and Keywords
Presentation 2023-03-25 14:05
Design of Decoded Instruction Cache
Takero Magara, Nobuyuki Yamasaki (Keio Univ.) CPSY2022-52 DC2022-111
Abstract (in Japanese) (See Japanese page) 
(in English) In Intel x86 processors, instructions are decoded into instructions for the internal RISC engine, called Micro-Operation (uOP) , and then executed. Once decoded, the μ OP is stored in the μ OP Cache. When it is used again, the power consumption is reduced and the performance is improved by eliminating the fetch and decode processes. In addition, the performance is further improved by dispatching with a wider bandwidth than that of the decoder. On the other hand, in RISC processors, instructions are decoded into control signals. Since this control signal is not stored anywhere, the result of decoding cannot be reused. Therefore, in this study, we designed the Decoded Instruction Cache (DIC) as a uOP Cache for RISC processors. The control signals generated by the decoding are combined into Decoded Instruction and stored in DIC. The fetch and decode processes are omitted and the Decoded Instruction is dispatched, which is expected to reduce power consumption and improve performance. In this paper, we introduced the DIC into the Responsive MultiThreaded Processor (RMTP).
Keyword (in Japanese) (See Japanese page) 
(in English) Micro-Operation Cache / Decoded Instruction / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 122, no. 451, CPSY2022-52, pp. 106-111, March 2023.
Paper # CPSY2022-52 
Date of Issue 2023-03-16 (CPSY, DC) 
ISSN Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2022-52 DC2022-111

Conference Information
Committee DC CPSY IPSJ-SLDM IPSJ-EMB IPSJ-ARC  
Conference Date 2023-03-23 - 2023-03-25 
Place (in Japanese) (See Japanese page) 
Place (in English) Amagi Town Disaster Prevention Center (Tokunoshima) 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To CPSY 
Conference Code 2023-03-DC-CPSY-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design of Decoded Instruction Cache 
Sub Title (in English)  
Keyword(1) Micro-Operation Cache  
Keyword(2) Decoded Instruction  
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1st Author's Name Takero Magara  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Nobuyuki Yamasaki  
2nd Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2023-03-25 14:05:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2022-52, DC2022-111 
Volume (vol) vol.122 
Number (no) no.451(CPSY), no.452(DC) 
Page pp.106-111 
#Pages 6 
Date of Issue 2023-03-16 (CPSY, DC) 

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