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| Presentation | 2023-04-11 09:30 [Invited Lecture] Development of A Variation-Tolerant Processing-In-Memory Architecture Using Discharging Current Calibration Daiki Kitagata, Shinji Tanaka, Naoya Fujita, Naoaki Irie (REL)  ICD2023-8 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Processing-in-memory (PIM) has recently been expected to be a key technology for endpoint intelligence since it can dramatically improve the energy efficiency of AI accelerators. Especially for analog PIM macros, circuit techniques for the reduction of MAC operation errors caused by PVT variation are highly important. Based on this background, we develop new variation-tolerant PIM architectures. The memory cell array in the macro consists of adjustable current ternary bit cell with redundant current paths. Discharging currents of all the cells are adjusted to an almost identical value with the proposed calibration sequence. Furthermore, each column in the memory array is divided into 4 sections and sequential MAC operations for the sections are performed when the number of discharging cells are large. The cycle overhead caused by the sequential operations can be reduced by skipping unneeded A/D conversion cycles. The proposed PIM macro and architectures demonstrate great variation immunity in 22nm process technology and several tens of TOPS/W can be achieved from the analysis of the measured power and HSPICE simulation. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | AI accelerator / deep neural network / processing-in-memory / SRAM / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 123, no. 1, ICD2023-8, pp. 16-16, April 2023. | |
| Paper # | ICD2023-8 | |
| Date of Issue | 2023-04-03 (ICD) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ICD2023-8 |
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| Conference Information | |
| Committee | ICD |
| Conference Date | 2023-04-10 - 2023-04-11 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2023-04-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of A Variation-Tolerant Processing-In-Memory Architecture Using Discharging Current Calibration |
| Sub Title (in English) | |
| Keyword(1) | AI accelerator |
| Keyword(2) | deep neural network |
| Keyword(3) | processing-in-memory |
| Keyword(4) | SRAM |
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| Keyword(8) | |
| 1st Author's Name | Daiki Kitagata |
| 1st Author's Affiliation | Renesas Electronics Corporation (REL) |
| 2nd Author's Name | Shinji Tanaka |
| 2nd Author's Affiliation | Renesas Electronics Corporation (REL) |
| 3rd Author's Name | Naoya Fujita |
| 3rd Author's Affiliation | Renesas Electronics Corporation (REL) |
| 4th Author's Name | Naoaki Irie |
| 4th Author's Affiliation | Renesas Electronics Corporation (REL) |
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| Speaker | Author-1 |
| Date Time | 2023-04-11 09:30:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | ICD2023-8 |
| Volume (vol) | vol.123 |
| Number (no) | no.1 |
| Page | p.16 |
| #Pages | 1 |
| Date of Issue | 2023-04-03 (ICD) |
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