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Paper Abstract and Keywords
Presentation 2023-08-04 18:20
Power Evaluation of "SLMLET" Chip with Mixed RISC-V MP and SLM Reconfiguration Logic
Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ./JST PRESTO), Hayate Okuhara (NUS), Hideharu Amano (Keio Univ.), Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) CPSY2023-25 DC2023-25
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, opportunities requiring processing at the IoT edge have been increasing. As a solution, not only conventional CPUs, FPGAs, and ASICs, SoCs using eFPGAs, which can be embedded in the same silicon as CPUs, are attracting attention.
Based on this, we have developed SLMLET, a compact and low-power-consumption SoC for IoT edge devices that combines RISC-V microprocessor IP, SLM (Scalable Logic Module) reconfiguration logic developed by Kumamoto University as an eFPGA, and high-speed Interface to ensure scalability. SLMLET, a SoC for small and low-power IoT edge devices, was developed and manufactured using the USJC 55nm process.
This paper introduces the features of this chip and the process used to manufacture it, and shows the leakage power and power consumption when the chip is actually loaded as an evaluation using an actual chip. As a result, we confirmed that it is possible to significantly reduce power consumption by setting not only the voltage but also the appropriate body bias according to the drive frequency, and we also confirmed that the leakage power of the chip is about 2.5mW at 0.55V VDD and -0.4V back bias, and that the package power of the chip with the CPU and I/F parts loaded is about 30MHz. In addition, it was also confirmed that the package power of the chip can be approximately 17.7mW at 30MHz clock, VDD 0.55V, and back bias -0.4V when the CPU and I/F parts are loaded.
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Reference Info. IEICE Tech. Rep., vol. 123, no. 145, CPSY2023-25, pp. 100-105, Aug. 2023.
Paper # CPSY2023-25 
Date of Issue 2023-07-26 (CPSY, DC) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2023-25 DC2023-25

Conference Information
Committee CPSY DC IPSJ-ARC  
Conference Date 2023-08-02 - 2023-08-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Hakodate Arena 
Topics (in Japanese) (See Japanese page) 
Topics (in English) SWoPP2023: Parallel, Distributed and Cooperative Processing Systems and Dependable Computing 
Paper Information
Registration To CPSY 
Conference Code 2023-08-CPSY-DC-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Power Evaluation of "SLMLET" Chip with Mixed RISC-V MP and SLM Reconfiguration Logic 
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1st Author's Name Yosuke Yanai  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Takuya Kojima  
2nd Author's Affiliation Tokyo University/JST PRESTO (Tokyo Univ./JST PRESTO)
3rd Author's Name Hayate Okuhara  
3rd Author's Affiliation National University of Singapore (NUS)
4th Author's Name Hideharu Amano  
4th Author's Affiliation Keio University (Keio Univ.)
5th Author's Name Morihiro Kuga  
5th Author's Affiliation Kumamoto University (Kumamoto Univ.)
6th Author's Name Masahiro Iida  
6th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Speaker Author-2 
Date Time 2023-08-04 18:20:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2023-25, DC2023-25 
Volume (vol) vol.123 
Number (no) no.145(CPSY), no.146(DC) 
Page pp.100-105 
#Pages 6 
Date of Issue 2023-07-26 (CPSY, DC) 

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