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Paper Abstract and Keywords
Presentation 2023-08-04 15:35
Improving Data Transfer Efficiency in Many-Core Systems with a RISC-V ISA Extension
Masaru Nishimura, Yuxi Tan, Yoshiki Yamaguchi (Tsukuba Univ.) RECONF2023-16
Abstract (in Japanese) (See Japanese page) 
(in English) The difficulty of balancing usability and efficient use of PEs and insufficient memory bandwidth are major issues for many-core processors. We have introduced DIMD (Dual Instruction Multiple-Data), a processing format with characteristics intermediate between SIMD and MIMD, to many-core processors, and confirmed the improvement of computational efficiency.
In this paper, we aim to achieve high data transfer efficiency on many-core processors by introducing a interconnect and a memory hierarchical structure based on HBM. The RISC-V ISA is adopted as the ISA of the PE (Processing Element), and various data exchanges are supported by a custom instruction set. Interconnect topology will also be improved to confirm the feasibility of even larger-scale many-core processors.
Keyword (in Japanese) (See Japanese page) 
(in English) many-core processor / micro architecture / SIMD / DIMD / RISC-V ISA / FPGA / HBM /  
Reference Info. IEICE Tech. Rep., vol. 123, no. 151, RECONF2023-16, pp. 13-18, Aug. 2023.
Paper # RECONF2023-16 
Date of Issue 2023-07-28 (RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2023-16

Conference Information
Committee RECONF  
Conference Date 2023-08-04 - 2023-08-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Hakodate Arena 
Topics (in Japanese) (See Japanese page) 
Topics (in English) SWoPP2023: Parallel, Distributed and Cooperative Processing Systems and Dependable Computing 
Paper Information
Registration To RECONF 
Conference Code 2023-08-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Improving Data Transfer Efficiency in Many-Core Systems with a RISC-V ISA Extension 
Sub Title (in English)  
Keyword(1) many-core processor  
Keyword(2) micro architecture  
Keyword(3) SIMD  
Keyword(4) DIMD  
Keyword(5) RISC-V ISA  
Keyword(6) FPGA  
Keyword(7) HBM  
Keyword(8)  
1st Author's Name Masaru Nishimura  
1st Author's Affiliation University of Tsukuba (Tsukuba Univ.)
2nd Author's Name Yuxi Tan  
2nd Author's Affiliation University of Tsukuba (Tsukuba Univ.)
3rd Author's Name Yoshiki Yamaguchi  
3rd Author's Affiliation University of Tsukuba (Tsukuba Univ.)
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Speaker Author-1 
Date Time 2023-08-04 15:35:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2023-16 
Volume (vol) vol.123 
Number (no) no.151 
Page pp.13-18 
#Pages 6 
Date of Issue 2023-07-28 (RECONF) 

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