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Paper Abstract and Keywords
Presentation 2023-08-08 15:15
Design and Implementation of Neuron Circuit Using Adiabatic Quantum-Flux-Parametron Logic
Tomoharu Yamauchi, Hao San (Tokyo City Univ.), Naoki Takeuchi (AIST/Yokohama National Univ.), Nobuyuki Yoshikawa (Yokohama National Univ.), Olivia Chen (Tokyo City Univ.) SCE2023-11
Abstract (in Japanese) (See Japanese page) 
(in English) Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient,high performance information processing systems. It is a low power dissipation circuits in superconducting digital circuits.In this paper,we proposed a binary neural network (BNN) to achieve low power dissipation and small area, and designed and implemented a neuron circuit that introduces analog operations using magnetic coupling-based confluence. To effectively solve the memory problem in neural networks using superconducting integrated circuits. As an operational demonstration, we designed and implemented 4, 8 and 16 input neuron circuits using AIST $mathrm{10,kA/cm^2}$ 4-layer Nb process,and confirmed their operation from low-speed measurements at $mathrm{100,kHz}$.
Keyword (in Japanese) (See Japanese page) 
(in English) adiabatic logic / superconducting digital circuits / AQFP / binary neural network / / / /  
Reference Info. IEICE Tech. Rep., vol. 123, no. 153, SCE2023-11, pp. 53-57, Aug. 2023.
Paper # SCE2023-11 
Date of Issue 2023-08-01 (SCE) 
ISSN Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee SCE  
Conference Date 2023-08-08 - 2023-08-08 
Place (in Japanese) (See Japanese page) 
Place (in English) Yokohama National Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SCE 
Conference Code 2023-08-SCE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design and Implementation of Neuron Circuit Using Adiabatic Quantum-Flux-Parametron Logic 
Sub Title (in English)  
Keyword(1) adiabatic logic  
Keyword(2) superconducting digital circuits  
Keyword(3) AQFP  
Keyword(4) binary neural network  
1st Author's Name Tomoharu Yamauchi  
1st Author's Affiliation Tokyo City University (Tokyo City Univ.)
2nd Author's Name Hao San  
2nd Author's Affiliation Tokyo City University (Tokyo City Univ.)
3rd Author's Name Naoki Takeuchi  
3rd Author's Affiliation National Institute of Advanced Industrial Science and Technology/Yokohama National University (AIST/Yokohama National Univ.)
4th Author's Name Nobuyuki Yoshikawa  
4th Author's Affiliation Yokohama National University (Yokohama National Univ.)
5th Author's Name Olivia Chen  
5th Author's Affiliation Tokyo City University (Tokyo City Univ.)
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Speaker Author-1 
Date Time 2023-08-08 15:15:00 
Presentation Time 25 minutes 
Registration for SCE 
Paper # SCE2023-11 
Volume (vol) vol.123 
Number (no) no.153 
Page pp.53-57 
Date of Issue 2023-08-01 (SCE) 

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