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Paper Abstract and Keywords
Presentation 2023-11-15 14:40
A 183.4 nJ/inference 152.8 µW Single-Chip Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application
Rei Sumikawa, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda (UTokyo) VLD2023-39 ICD2023-47 DC2023-46 RECONF2023-42
Abstract (in Japanese) (See Japanese page) 
(in English) A 183.4-nJ/inference single-chip wired-logic DNN processor that is capable of recognizing all 35 commands defined in the industrial standard voice recognition data set (Google Speech Command Dataset) is developed. The algorithm-circuit co-optimized processor recognizes 3.5 times more commands with 1.6 times higher energy efficiency than the state-of-the-art analog processor while keeping design cost low. By implementing all the processing circuits and wiring required for the 16-layer DNN onto a single chip, the need to store weight coefficients and intermediate data in DRAM/SRAM is eliminated. Owing to the proposed architecture, a low power consumption of 152.8 µW is achieved, which is low enough for always-on applications on battery-powered IoT devices.
Keyword (in Japanese) (See Japanese page) 
(in English) DNN / AI processor / Wired-logic / Algorithm-circuit co-optimization / / / /  
Reference Info. IEICE Tech. Rep., vol. 123, no. 259, ICD2023-47, pp. 54-59, Nov. 2023.
Paper # ICD2023-47 
Date of Issue 2023-11-08 (VLD, ICD, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2023-39 ICD2023-47 DC2023-46 RECONF2023-42

Conference Information
Committee VLD DC RECONF ICD IPSJ-SLDM  
Conference Date 2023-11-15 - 2023-11-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Civic Auditorium Sears Home Yume Hall 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2023 -New Field of VLSI Design- 
Paper Information
Registration To ICD 
Conference Code 2023-11-VLD-DC-RECONF-ICD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A 183.4 nJ/inference 152.8 µW Single-Chip Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application 
Sub Title (in English)  
Keyword(1) DNN  
Keyword(2) AI processor  
Keyword(3) Wired-logic  
Keyword(4) Algorithm-circuit co-optimization  
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1st Author's Name Rei Sumikawa  
1st Author's Affiliation The University of Tokyo (UTokyo)
2nd Author's Name Atsutake Kosuge  
2nd Author's Affiliation The University of Tokyo (UTokyo)
3rd Author's Name Mototsugu Hamada  
3rd Author's Affiliation The University of Tokyo (UTokyo)
4th Author's Name Tadahiro Kuroda  
4th Author's Affiliation The University of Tokyo (UTokyo)
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Speaker Author-1 
Date Time 2023-11-15 14:40:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # VLD2023-39, ICD2023-47, DC2023-46, RECONF2023-42 
Volume (vol) vol.123 
Number (no) no.258(VLD), no.259(ICD), no.260(DC), no.261(RECONF) 
Page pp.54-59 
#Pages 6 
Date of Issue 2023-11-08 (VLD, ICD, DC, RECONF) 

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