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Paper Abstract and Keywords
Presentation 2024-01-29 10:55
Suppression of output bit width growth in AFE stochastic computing units
Daiki Seto, Naoki Fujieda (Aichi Inst. Tech.) VLD2023-81 RECONF2023-84
Abstract (in Japanese) (See Japanese page) 
(in English) Stochastic Computing (SC) is expected to be applied to fields such as image processing and machine learning. Amplitude and Frequency Encoding (AFE) is a new encoding method for SC. However, it has a drawback that the output bit width grows when cascading AFE SC operators. This paper proposes two types of correction circuits, F-Corrector and S-Corrector, and implements new AFE SC operators that suppress the growth of output bit-width. The results of the evaluation using the PYNQ-Z1 board showed that the arithmetic error of the proposed AFE SC operators was the same as or less than that of the conventional AFE SC operators.
Keyword (in Japanese) (See Japanese page) 
(in English) Digital Circuit Design / Stochastic Computing / AFE (Amplitude and Frequency Encoding) / FPGA (Field-Programmable Gate Array) / / / /  
Reference Info. IEICE Tech. Rep., vol. 123, no. 374, RECONF2023-84, pp. 7-12, Jan. 2024.
Paper # RECONF2023-84 
Date of Issue 2024-01-22 (VLD, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2023-81 RECONF2023-84

Conference Information
Committee RECONF VLD  
Conference Date 2024-01-29 - 2024-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English) AIRBIC Meeting Room 1-4 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To RECONF 
Conference Code 2024-01-RECONF-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Suppression of output bit width growth in AFE stochastic computing units 
Sub Title (in English)  
Keyword(1) Digital Circuit Design  
Keyword(2) Stochastic Computing  
Keyword(3) AFE (Amplitude and Frequency Encoding)  
Keyword(4) FPGA (Field-Programmable Gate Array)  
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1st Author's Name Daiki Seto  
1st Author's Affiliation Aichi Institute of Technology (Aichi Inst. Tech.)
2nd Author's Name Naoki Fujieda  
2nd Author's Affiliation Aichi Institute of Technology (Aichi Inst. Tech.)
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Speaker Author-1 
Date Time 2024-01-29 10:55:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2023-81, RECONF2023-84 
Volume (vol) vol.123 
Number (no) no.373(VLD), no.374(RECONF) 
Page pp.7-12 
#Pages 6 
Date of Issue 2024-01-22 (VLD, RECONF) 

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