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Paper Abstract and Keywords
Presentation 2024-01-29 17:00
Derivation of an Evaluation Chip Spec suitable for Tester and Data Analysis -- Toward comparative evaluation of latch-based and flip-flop-based circuits --
Tadaaki Tanimoto, Keizo Hiraga, Toshihiko Katou, Kazuhiro Bessho, Toshimasa Shimizu (Sony Semiconductor Solutions) VLD2023-90 RECONF2023-93
Abstract (in Japanese) (See Japanese page) 
(in English) As a synchronous logic circuit, it is often argued that latch-based circuits are superior to flip-flop circuits in terms of low power consumption and high-speed frequency characteristics. There are reports on simulations, but as far as we know, there are no comparison results with actual chips. Although it is possible to set any observation point in simulation evaluation, this is generally difficult to achieve in actual chip evaluation, so it is necessary to evaluate only input/output operations. Therefore, in this article, for the purpose of comparing characteristics based only on input/output operations, we will explain the specifications and evaluation chips that were derived by taking tester measurements and data analysis into consideration.
Keyword (in Japanese) (See Japanese page) 
(in English) Flip-flop based circuits / Latch-based circuits / Tester measurement / Data pipeline / Data analysis / / /  
Reference Info. IEICE Tech. Rep., vol. 123, no. 373, VLD2023-90, pp. 59-64, Jan. 2024.
Paper # VLD2023-90 
Date of Issue 2024-01-22 (VLD, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2023-90 RECONF2023-93

Conference Information
Committee RECONF VLD  
Conference Date 2024-01-29 - 2024-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English) AIRBIC Meeting Room 1-4 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To VLD 
Conference Code 2024-01-RECONF-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Derivation of an Evaluation Chip Spec suitable for Tester and Data Analysis 
Sub Title (in English) Toward comparative evaluation of latch-based and flip-flop-based circuits 
Keyword(1) Flip-flop based circuits  
Keyword(2) Latch-based circuits  
Keyword(3) Tester measurement  
Keyword(4) Data pipeline  
Keyword(5) Data analysis  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Tadaaki Tanimoto  
1st Author's Affiliation Sony Semiconductor Solutions, Corporation (Sony Semiconductor Solutions)
2nd Author's Name Keizo Hiraga  
2nd Author's Affiliation Sony Semiconductor Solutions, Corporation (Sony Semiconductor Solutions)
3rd Author's Name Toshihiko Katou  
3rd Author's Affiliation Sony Semiconductor Solutions, Corporation (Sony Semiconductor Solutions)
4th Author's Name Kazuhiro Bessho  
4th Author's Affiliation Sony Semiconductor Solutions, Corporation (Sony Semiconductor Solutions)
5th Author's Name Toshimasa Shimizu  
5th Author's Affiliation Sony Semiconductor Solutions, Corporation (Sony Semiconductor Solutions)
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Speaker Author-1 
Date Time 2024-01-29 17:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2023-90, RECONF2023-93 
Volume (vol) vol.123 
Number (no) no.373(VLD), no.374(RECONF) 
Page pp.59-64 
#Pages 6 
Date of Issue 2024-01-22 (VLD, RECONF) 

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