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| Presentation | 2024-01-30 13:20 Reduction of Circuit Size by Optimizing Status Registers in Full Hardware RTOS-Based Systems Kei Mikami, Nagisa Ishiura (Kansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM)  VLD2023-94 RECONF2023-97 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This article presents a technique for handling increased number of tasks by reducing both circuit size and critical path delay, within the context of full hardware implementation of RTOS-based systems. Oosako and Muguruma previously proposed methods to enhance the response performance of real-time systems by implementing both tasks/handlers and RTOS kernel functions as hardware. However, their methods assume around 8 tasks, and surpassing this count results in impractical circuit size and critical path delay. In our work, we address these scalability challenges by adopting a more efficient circuit design. This involves reducing the bit count of state registers responsible for storing task states and integrating them into a single register per task. Additionally, we control the critical path delay by multi-stage implementation of the service request arbitration circuit. We have designed a management module that incorporates RTOS functions for 64 tasks based on our proposed method. This design has led to a substantial reduction in circuit size, approximately 48%, and a decrease in critical path delay by around 55% when compared to the previous design. Furthermore, we have observed an average reduction of approximately 1 cycle in the number of execution cycles from the initiation of a task requesting service processing to receiving the return value. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Real-Time Systems / RTOS / System Synthesis / Hardware Accelerator / TOPPERS/ASP3 / High-Level Synthesis / / | |
| Reference Info. | IEICE Tech. Rep., vol. 123, no. 373, VLD2023-94, pp. 81-86, Jan. 2024. | |
| Paper # | VLD2023-94 | |
| Date of Issue | 2024-01-22 (VLD, RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2023-94 RECONF2023-97 |
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| Conference Information | |
| Committee | RECONF VLD |
| Conference Date | 2024-01-29 - 2024-01-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | AIRBIC Meeting Room 1-4 |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2024-01-RECONF-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Reduction of Circuit Size by Optimizing Status Registers in Full Hardware RTOS-Based Systems |
| Sub Title (in English) | |
| Keyword(1) | Real-Time Systems |
| Keyword(2) | RTOS |
| Keyword(3) | System Synthesis |
| Keyword(4) | Hardware Accelerator |
| Keyword(5) | TOPPERS/ASP3 |
| Keyword(6) | High-Level Synthesis |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kei Mikami |
| 1st Author's Affiliation | Kwansei Gakuin University (Kansei Gakuin Univ.) |
| 2nd Author's Name | Nagisa Ishiura |
| 2nd Author's Affiliation | Kwansei Gakuin University (Kansei Gakuin Univ.) |
| 3rd Author's Name | Hiroyuki Tomiyama |
| 3rd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 4th Author's Name | Hiroyuki Kanbara |
| 4th Author's Affiliation | Advanced Science, Technology & Management Research Institute of KYOTO (ASTEM) |
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| Speaker | Author-1 |
| Date Time | 2024-01-30 13:20:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2023-94, RECONF2023-97 |
| Volume (vol) | vol.123 |
| Number (no) | no.373(VLD), no.374(RECONF) |
| Page | pp.81-86 |
| #Pages | 6 |
| Date of Issue | 2024-01-22 (VLD, RECONF) |
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