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Paper Abstract and Keywords
Presentation 2024-01-30 13:45
Implementation of External Memory Access for Binary Synthesis Using General-Purpose High-Level Synthesizer
Sho Kishimoto, Nagisa Ishiukra (Kwansei Gakuin Univ.) VLD2023-95 RECONF2023-98
Abstract (in Japanese) (See Japanese page) 
(in English) In this article, we present a method for implementing external memory access within the context of binary synthesis utilizing commercial high-level synthesis systems. Binary synthesis, which translates binary program codes into hardware designs, enables synthesis of hardware from programs using assembly or inline assembly. Nakamichi et al. has proposed an approach for facilitating implementation of binary synthezers, in which binary programs are once translated into C programs and then processed by a high-level synthezer. However, binary synthesizers developed so far using this method embed memory within the synthesized hardware, thereby impeding data sharing among various hardware components and memory-mapped I/O. This paper aims to enhance Nakamichi's method to enable external memory access through I/O ports of synthesized hardware, facilitating memory-mapped I/O as well. A binary synthesizer, implemented based on the proposed method, demonstrates that external memory access and memory-mapped I/O are achievable without incurring significant overhead in terms of circuit size and execution cycle count.
Keyword (in Japanese) (See Japanese page) 
(in English) Binary synthesis / High-level synthesis / RISC-V / ISA / Embedded system / / /  
Reference Info. IEICE Tech. Rep., vol. 123, no. 373, VLD2023-95, pp. 87-92, Jan. 2024.
Paper # VLD2023-95 
Date of Issue 2024-01-22 (VLD, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2023-95 RECONF2023-98

Conference Information
Committee RECONF VLD  
Conference Date 2024-01-29 - 2024-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English) AIRBIC Meeting Room 1-4 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To VLD 
Conference Code 2024-01-RECONF-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation of External Memory Access for Binary Synthesis Using General-Purpose High-Level Synthesizer 
Sub Title (in English)  
Keyword(1) Binary synthesis  
Keyword(2) High-level synthesis  
Keyword(3) RISC-V  
Keyword(4) ISA  
Keyword(5) Embedded system  
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Keyword(7)  
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1st Author's Name Sho Kishimoto  
1st Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
2nd Author's Name Nagisa Ishiukra  
2nd Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
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Speaker Author-1 
Date Time 2024-01-30 13:45:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2023-95, RECONF2023-98 
Volume (vol) vol.123 
Number (no) no.373(VLD), no.374(RECONF) 
Page pp.87-92 
#Pages 6 
Date of Issue 2024-01-22 (VLD, RECONF) 

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