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| Presentation | 2024-02-21 10:45 [Invited Talk] Development of Superconducting Nb Interconnects for Low-Temperature SoC for Qubit Control Hideaki Numata, Noriyuki Iguchi (NBS), Masamitsu Tanaka (Nagoya Univ.), Koichiro Okamoto, Sadahiko Miura (NBS), Ken Uchida (UTokyo), Hiroki Ishikuro (Keio Univ.), Toshitsugu Sakamoto, Munehiro Tada (NBS)  SDM2023-82 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A 100 nm wide superconducting Nb interconnects were fabricated by a 300-mm wafer process for low temperature SoC applications. A low pressure and long throw sputtering was adopted for the Nb deposition, resulting in good superconductivity of the 50 nm thick Nb film with a critical temperature (Tc) of 8.3 K. The interconnects had a TiN/Nb stack structure, and a double layer hard mask was used for dry etching process. The 25 nm TiN layer well protected the Nb film from plasma damage during the fabrication, then the developed 100 nm wide Nb interconnect showed good superconductivity with a Tc of 7.8 K and a critical current of 3.2 mA at 4.2 K. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Superconductor / Nb / Interconnect / Dry Etching / Cryo-CMOS / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 123, no. 385, SDM2023-82, pp. 4-8, Feb. 2024. | |
| Paper # | SDM2023-82 | |
| Date of Issue | 2024-02-14 (SDM) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2023-82 |
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| Conference Information | |
| Committee | SDM |
| Conference Date | 2024-02-21 - 2024-02-21 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Tokyo University-Hongo-Engineering Bldg.4 |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | SDM |
| Conference Code | 2024-02-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of Superconducting Nb Interconnects for Low-Temperature SoC for Qubit Control |
| Sub Title (in English) | |
| Keyword(1) | Superconductor |
| Keyword(2) | Nb |
| Keyword(3) | Interconnect |
| Keyword(4) | Dry Etching |
| Keyword(5) | Cryo-CMOS |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Hideaki Numata |
| 1st Author's Affiliation | NanoBridge Semiconductor, Inc. (NBS) |
| 2nd Author's Name | Noriyuki Iguchi |
| 2nd Author's Affiliation | NanoBridge Semiconductor, Inc. (NBS) |
| 3rd Author's Name | Masamitsu Tanaka |
| 3rd Author's Affiliation | Nagoya University (Nagoya Univ.) |
| 4th Author's Name | Koichiro Okamoto |
| 4th Author's Affiliation | NanoBridge Semiconductor, Inc. (NBS) |
| 5th Author's Name | Sadahiko Miura |
| 5th Author's Affiliation | NanoBridge Semiconductor, Inc. (NBS) |
| 6th Author's Name | Ken Uchida |
| 6th Author's Affiliation | The University of Tokyo (UTokyo) |
| 7th Author's Name | Hiroki Ishikuro |
| 7th Author's Affiliation | Keio University (Keio Univ.) |
| 8th Author's Name | Toshitsugu Sakamoto |
| 8th Author's Affiliation | NanoBridge Semiconductor, Inc. (NBS) |
| 9th Author's Name | Munehiro Tada |
| 9th Author's Affiliation | NanoBridge Semiconductor, Inc. (NBS) |
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| Speaker | Author-1 |
| Date Time | 2024-02-21 10:45:00 |
| Presentation Time | 40 minutes |
| Registration for | SDM |
| Paper # | SDM2023-82 |
| Volume (vol) | vol.123 |
| Number (no) | no.385 |
| Page | pp.4-8 |
| #Pages | 5 |
| Date of Issue | 2024-02-14 (SDM) |
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