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Paper Abstract and Keywords
Presentation 2024-02-29 11:15
Design of RISC-V SoC with Post-quantum Encryption Algorithm Acceleration
Jiyuan Xin, Makoto Ikeda (UTokyo) VLD2023-110 HWS2023-70 ICD2023-99
Abstract (in Japanese) (See Japanese page) 
(in English) The foundational elements of the Internet of Things (IoT) are increasingly intricate and robust Systems-on-Chips (SoCs) seamlessly linked through advanced networks. This interconnected infrastructure serves as the catalyst for digital transformation across diverse domains, including industry automation, automotive, avionics, and healthcare. Also, because of the emergence of open-source RISC-V, anyone can design processors based on own needs for free, which leads SoC development more vigorous. However, the foreseeable advent of quantum computers introduces a looming risk to communication security. In the field of public-key cryptography, there is concern that existing public-key cryptography, will be compromised by quantum computers. For this reason, many studies are progressing on post-quantum cryptography (PQC), which is cryptography that cannot be solved in polynomial time, even by a quantum computer. In this paper, we proposed a RISC-V co-processor embedded with PQC algorithm hardware accelerator, which could significantly improve the speed of cryptographic computation on it.
Keyword (in Japanese) (See Japanese page) 
(in English) RISC-V / Public Key Encryption / Post-quantum Encryption / Hardware Accelerator / / / /  
Reference Info. IEICE Tech. Rep., vol. 123, no. 392, ICD2023-99, pp. 66-71, Feb. 2024.
Paper # ICD2023-99 
Date of Issue 2024-02-21 (VLD, HWS, ICD) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2023-110 HWS2023-70 ICD2023-99

Conference Information
Committee VLD HWS ICD  
Conference Date 2024-02-28 - 2024-03-02 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2024-02-VLD-HWS-ICD 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design of RISC-V SoC with Post-quantum Encryption Algorithm Acceleration 
Sub Title (in English)  
Keyword(1) RISC-V  
Keyword(2) Public Key Encryption  
Keyword(3) Post-quantum Encryption  
Keyword(4) Hardware Accelerator  
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Keyword(6)  
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Keyword(8)  
1st Author's Name Jiyuan Xin  
1st Author's Affiliation The University of Tokyo (UTokyo)
2nd Author's Name Makoto Ikeda  
2nd Author's Affiliation The University of Tokyo (UTokyo)
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Speaker Author-1 
Date Time 2024-02-29 11:15:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # VLD2023-110, HWS2023-70, ICD2023-99 
Volume (vol) vol.123 
Number (no) no.390(VLD), no.391(HWS), no.392(ICD) 
Page pp.66-71 
#Pages 6 
Date of Issue 2024-02-21 (VLD, HWS, ICD) 

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