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Paper Abstract and Keywords
Presentation 2024-02-29 15:55
[Memorial Lecture] Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits
Kazuki Minamiguchi, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi (Osaka Univ.) VLD2023-117 HWS2023-77 ICD2023-106
Abstract (in Japanese) (See Japanese page) 
(in English) The threat of information leakage by Side-Channel Attacks (SCAs) using ElectroMagnetic (EM) leakage is becoming more and more prominent for crypto circuits. This paper models tamper resistance to EM SCAs on voltage-scaled crypto circuits. It is well know that if the supply voltage is donwscaled, attackers need to acquire more EM traces to extract secret key information in crypto circuits. Therefore, crypto circuits can process more data safely. However, their supply voltage dependence is not fully studied. This paper thus firstly models voltage dependence of the strength in the EM emission from crypto circuits. Then, this paper models the tamper resistance which analytically expresses the relationship between the necessary number of EM traces and the supply voltage. This helps consider to optimize the trade-off relationship between encryption performance and tamper resistance to the information leakage. The proposed models are validated by measurement results using an Advanced Encryption Standard (AES) circuit with a 180-nm process technology.
Keyword (in Japanese) (See Japanese page) 
(in English) Electromagnetic leakage / side-channel attack / voltage-scaled circuit design / / / / /  
Reference Info. IEICE Tech. Rep., vol. 123, no. 390, VLD2023-117, pp. 99-99, Feb. 2024.
Paper # VLD2023-117 
Date of Issue 2024-02-21 (VLD, HWS, ICD) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2023-117 HWS2023-77 ICD2023-106

Conference Information
Committee VLD HWS ICD  
Conference Date 2024-02-28 - 2024-03-02 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2024-02-VLD-HWS-ICD 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits 
Sub Title (in English)  
Keyword(1) Electromagnetic leakage  
Keyword(2) side-channel attack  
Keyword(3) voltage-scaled circuit design  
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1st Author's Name Kazuki Minamiguchi  
1st Author's Affiliation Osaka University (Osaka Univ.)
2nd Author's Name Yoshihiro Midoh  
2nd Author's Affiliation Osaka University (Osaka Univ.)
3rd Author's Name Noriyuki Miura  
3rd Author's Affiliation Osaka University (Osaka Univ.)
4th Author's Name Jun Shiomi  
4th Author's Affiliation Osaka University (Osaka Univ.)
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Speaker Author-1 
Date Time 2024-02-29 15:55:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2023-117, HWS2023-77, ICD2023-106 
Volume (vol) vol.123 
Number (no) no.390(VLD), no.391(HWS), no.392(ICD) 
Page p.99 
#Pages 1 
Date of Issue 2024-02-21 (VLD, HWS, ICD) 

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