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| Presentation | 2024-03-01 16:20 An Efficient Hardware Approach for High-Speed SPHINCS+ Signature Generation Yuta Takeshima, Makoto Ikeda (The Univ. of Tokyo)  VLD2023-132 HWS2023-92 ICD2023-121 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This study addresses the challenges traditional cryptographic systems face with the advent of quantum computers by focusing on improving the processing speed of SPHINCS+, a hash-based digital signature algorithm. Despite its robustness and ongoing standardization, SPHINCS+ suffers from slow processing speeds, potentially limiting its real-time application use. By proposing a low-latency hardware design that utilizes multiple thash operators to accelerate FORS signature generation, the study demonstrates that increasing core counts can significantly reduce latency and the area-delay product, making this approach faster compared to other hardware implementations. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | SPHINCS+ / hash-based signature / Post-Quantum Cryptography / hardware / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 123, no. 391, HWS2023-92, pp. 173-177, Feb. 2024. | |
| Paper # | HWS2023-92 | |
| Date of Issue | 2024-02-21 (VLD, HWS, ICD) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2023-132 HWS2023-92 ICD2023-121 |
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| Conference Information | |
| Committee | VLD HWS ICD |
| Conference Date | 2024-02-28 - 2024-03-02 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | HWS |
| Conference Code | 2024-02-VLD-HWS-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Efficient Hardware Approach for High-Speed SPHINCS+ Signature Generation |
| Sub Title (in English) | |
| Keyword(1) | SPHINCS+ |
| Keyword(2) | hash-based signature |
| Keyword(3) | Post-Quantum Cryptography |
| Keyword(4) | hardware |
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| Keyword(6) | |
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| 1st Author's Name | Yuta Takeshima |
| 1st Author's Affiliation | The University of Tokyo (The Univ. of Tokyo) |
| 2nd Author's Name | Makoto Ikeda |
| 2nd Author's Affiliation | The University of Tokyo (The Univ. of Tokyo) |
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| Speaker | Author-1 |
| Date Time | 2024-03-01 16:20:00 |
| Presentation Time | 25 minutes |
| Registration for | HWS |
| Paper # | VLD2023-132, HWS2023-92, ICD2023-121 |
| Volume (vol) | vol.123 |
| Number (no) | no.390(VLD), no.391(HWS), no.392(ICD) |
| Page | pp.173-177 |
| #Pages | 5 |
| Date of Issue | 2024-02-21 (VLD, HWS, ICD) |
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