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Paper Abstract and Keywords
Presentation 2024-03-01 14:50
Defect Coverage Estimation by Sampling in Testing Power TSV
Koutaro Hachiya, Yudai Kawakami (THU) VLD2023-129 HWS2023-89 ICD2023-118
Abstract (in Japanese) (See Japanese page) 
(in English) As a test for power TSVs (Through Silicon Via) in 3D-IC, a method has been proposed to detect open defects by placing power pads directly under the TSVs and measuring the resistance between the power pads. Determining this test's defect coverage is time-consuming because it requires repeated circuit simulations to determine the resistance between the pads. Therefore, this paper proposes a method to estimate the defect coverage by sampling to speed up the process. Under experimental conditions, we could estimate the defect coverage with 1/10th of the computational complexity and a confidence interval width of 6.2-10.8%.
Keyword (in Japanese) (See Japanese page) 
(in English) 3D integrated circuits / through silicon via / open defect / defect coverage / confidence interval / / /  
Reference Info. IEICE Tech. Rep., vol. 123, no. 390, VLD2023-129, pp. 157-160, Feb. 2024.
Paper # VLD2023-129 
Date of Issue 2024-02-21 (VLD, HWS, ICD) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2023-129 HWS2023-89 ICD2023-118

Conference Information
Committee VLD HWS ICD  
Conference Date 2024-02-28 - 2024-03-02 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
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Paper Information
Registration To VLD 
Conference Code 2024-02-VLD-HWS-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Defect Coverage Estimation by Sampling in Testing Power TSV 
Sub Title (in English)  
Keyword(1) 3D integrated circuits  
Keyword(2) through silicon via  
Keyword(3) open defect  
Keyword(4) defect coverage  
Keyword(5) confidence interval  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Koutaro Hachiya  
1st Author's Affiliation Teikyo Heisei University (THU)
2nd Author's Name Yudai Kawakami  
2nd Author's Affiliation Teikyo Heisei University (THU)
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Speaker Author-1 
Date Time 2024-03-01 14:50:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2023-129, HWS2023-89, ICD2023-118 
Volume (vol) vol.123 
Number (no) no.390(VLD), no.391(HWS), no.392(ICD) 
Page pp.157-160 
#Pages 4 
Date of Issue 2024-02-21 (VLD, HWS, ICD) 

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