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Paper Abstract and Keywords
Presentation 2024-03-02 12:05
A Study on formal verification of GF(2^m) arithmetic circuits including states
Kazuho Sakoda (SCU/Kobe Univ.), Yasuyoshi Uemura (SCU), Naofumi Homma (Tohoku Univ.) VLD2023-140 HWS2023-100 ICD2023-129
Abstract (in Japanese) (See Japanese page) 
(in English) This paper describes a formal verification method for arithmetic circuits based on computer algebra. Conventional methods usually target only combinational circuits and have difficulty in applying to sequential circuits including control states. In this paper, we discuss an extension to enable the formal verification of such arithmetic sequential circuits. We show the validity of the proposed method through some experiments.
Keyword (in Japanese) (See Japanese page) 
(in English) formal verification / computer algebra / cryptography / Galois field arithmetic circuits / / / /  
Reference Info. IEICE Tech. Rep., vol. 123, no. 391, HWS2023-100, pp. 215-220, Feb. 2024.
Paper # HWS2023-100 
Date of Issue 2024-02-21 (VLD, HWS, ICD) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2023-140 HWS2023-100 ICD2023-129

Conference Information
Committee VLD HWS ICD  
Conference Date 2024-02-28 - 2024-03-02 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To HWS 
Conference Code 2024-02-VLD-HWS-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Study on formal verification of GF(2^m) arithmetic circuits including states 
Sub Title (in English)  
Keyword(1) formal verification  
Keyword(2) computer algebra  
Keyword(3) cryptography  
Keyword(4) Galois field arithmetic circuits  
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1st Author's Name Kazuho Sakoda  
1st Author's Affiliation SCU Co., Ltd./Kobe University (SCU/Kobe Univ.)
2nd Author's Name Yasuyoshi Uemura  
2nd Author's Affiliation SCU Co., Ltd. (SCU)
3rd Author's Name Naofumi Homma  
3rd Author's Affiliation Tohoku University (Tohoku Univ.)
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Speaker Author-1 
Date Time 2024-03-02 12:05:00 
Presentation Time 25 minutes 
Registration for HWS 
Paper # VLD2023-140, HWS2023-100, ICD2023-129 
Volume (vol) vol.123 
Number (no) no.390(VLD), no.391(HWS), no.392(ICD) 
Page pp.215-220 
#Pages 6 
Date of Issue 2024-02-21 (VLD, HWS, ICD) 

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