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| Presentation | 2024-03-22 10:15 Context Cache Design for Multicore RISC-V Processors Akira Yamazawa (Keio Univ), Tsutomu Itou, Suito Kazutoshi (AXELL), Nobuyuki Yamasaki (Keio Univ)  CPSY2023-44 DC2023-110 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Today, programs are executed using multiple threads. When multiple threads are used for execution, a context switch occurs when the threads are exchanged. The context switch saves the information necessary for the computation (context) to memory and retrieves the context of the next thread from memory. This process results in a large overhead. The context switch overhead can be reduced by using a on-chip cache, the context cache. In this study, we designed the context cache for multi-core RISC-V processors. The results were evaluated with and without the context cache. The proposed method reduces the overhead of context switches. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | RISC-C / Context switch / Multithread / Multicore / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 123, no. 450, CPSY2023-44, pp. 35-40, March 2024. | |
| Paper # | CPSY2023-44 | |
| Date of Issue | 2024-03-14 (CPSY, DC) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2023-44 DC2023-110 |
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| Conference Information | |
| Committee | DC CPSY IPSJ-SLDM IPSJ-EMB IPSJ-ARC |
| Conference Date | 2024-03-21 - 2024-03-23 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ikinoshima Hall |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | ETNET2024 |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2024-03-DC-CPSY-SLDM-EMB-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Context Cache Design for Multicore RISC-V Processors |
| Sub Title (in English) | |
| Keyword(1) | RISC-C |
| Keyword(2) | Context switch |
| Keyword(3) | Multithread |
| Keyword(4) | Multicore |
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| 1st Author's Name | Akira Yamazawa |
| 1st Author's Affiliation | Keio University (Keio Univ) |
| 2nd Author's Name | Tsutomu Itou |
| 2nd Author's Affiliation | Axell Corporation (AXELL) |
| 3rd Author's Name | Suito Kazutoshi |
| 3rd Author's Affiliation | Axell Corporation (AXELL) |
| 4th Author's Name | Nobuyuki Yamasaki |
| 4th Author's Affiliation | Keio University (Keio Univ) |
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| Speaker | Author-1 |
| Date Time | 2024-03-22 10:15:00 |
| Presentation Time | 25 minutes |
| Registration for | CPSY |
| Paper # | CPSY2023-44, DC2023-110 |
| Volume (vol) | vol.123 |
| Number (no) | no.450(CPSY), no.451(DC) |
| Page | pp.35-40 |
| #Pages | 6 |
| Date of Issue | 2024-03-14 (CPSY, DC) |
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