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Paper Abstract and Keywords
Presentation 2024-03-22 09:50
Integration of Vector Extension and Simultaneous Multithreading for a RISC-V Processor
Hidetaro Tanaka, Shogo Takata, Hironori Nakajo (TUAT) CPSY2023-43 DC2023-109
Abstract (in Japanese) (See Japanese page) 
(in English) In vector architectures, the potential for parallel execution lies in the chaining of instruction sequences. However, a singular instruction flow may lead to underutilization of vector functional units. The integration of Simultaneous Multithreading (SMT) presents an opportunity to enhance the efficiency of vector functional units, thereby expediting programs with high data-level parallelism, notably evident in AI applications, which have experienced higher demand recently. This study introduces B4SMT-V, a RISC-V Processor that integrates vector extension with SMT. Specifically, it extends the vector architecture onto B4SMT, a RISC-V SMT processor previously developed in 2022 in our laboratory. On matrix multiplication programs, SMT demonstrates a reduction in clock cycles approximately 53.8%, when compared with single thread execution. In addition, when compared with the same total size of vector register files, the use of SMT reduced the clock cycles to approximately 73.7%.
Keyword (in Japanese) (See Japanese page) 
(in English) RISC-V / Vector Architecture / SMT / AI / / / /  
Reference Info. IEICE Tech. Rep., vol. 123, no. 450, CPSY2023-43, pp. 29-34, March 2024.
Paper # CPSY2023-43 
Date of Issue 2024-03-14 (CPSY, DC) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2023-43 DC2023-109

Conference Information
Committee DC CPSY IPSJ-SLDM IPSJ-EMB IPSJ-ARC  
Conference Date 2024-03-21 - 2024-03-23 
Place (in Japanese) (See Japanese page) 
Place (in English) Ikinoshima Hall 
Topics (in Japanese) (See Japanese page) 
Topics (in English) ETNET2024 
Paper Information
Registration To CPSY 
Conference Code 2024-03-DC-CPSY-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Integration of Vector Extension and Simultaneous Multithreading for a RISC-V Processor 
Sub Title (in English)  
Keyword(1) RISC-V  
Keyword(2) Vector Architecture  
Keyword(3) SMT  
Keyword(4) AI  
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1st Author's Name Hidetaro Tanaka  
1st Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
2nd Author's Name Shogo Takata  
2nd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
3rd Author's Name Hironori Nakajo  
3rd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
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Speaker Author-1 
Date Time 2024-03-22 09:50:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2023-43, DC2023-109 
Volume (vol) vol.123 
Number (no) no.450(CPSY), no.451(DC) 
Page pp.29-34 
#Pages 6 
Date of Issue 2024-03-14 (CPSY, DC) 

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