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Paper Abstract and Keywords
Presentation 2024-04-12 13:50
[Invited Lecture] Development of a Bridge Chip for Scalable Performance and Capacity Storage Systems
Shinichi Ikeda, Akira Iwata, Goichi Otomo, Tomoaki Suzuki, Hiroaki Iijima, Mikio Shiraishi, Shinya Kawakami, Masatomo Eimitsu, Yoshiki Matsuoka, Kiyohito Sato, Shigehiro Tsuchiya, Yoshinori Shigeta, Takuma Aoyama (Kioxia) ICD2024-14
Abstract (in Japanese) (See Japanese page) 
(in English) We describe a Bridge Chip that enables a high-speed, high-capacity storage system. The proposed Bridge Chip employs a function to double the speed of the existing NAND interface, a Fast-Lock PLL with enhanced input jitter rejection, and an equalizer to eliminate reflection noise in a multi-drop configuration. NAND Flash Memory Multi-Chip Package incorporating both eight 1Tb NAND dies and a Bridge Chip fabricated in a 12nm CMOS process achieved an I/O energy efficiency of 2.85pJ/b in a read operation at an interface speed of 6.4Gbps/pin.
Keyword (in Japanese) (See Japanese page) 
(in English) NAND / Multi-Chip Package / Fast-Lock PLL / reflection canceling equalizer / frequency multiplying function / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 3, ICD2024-14, pp. 43-43, April 2024.
Paper # ICD2024-14 
Date of Issue 2024-04-04 (ICD) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2024-14

Conference Information
Committee ICD  
Conference Date 2024-04-11 - 2024-04-12 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2024-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Development of a Bridge Chip for Scalable Performance and Capacity Storage Systems 
Sub Title (in English)  
Keyword(1) NAND  
Keyword(2) Multi-Chip Package  
Keyword(3) Fast-Lock PLL  
Keyword(4) reflection canceling equalizer  
Keyword(5) frequency multiplying function  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Shinichi Ikeda  
1st Author's Affiliation Kioxia Corporation (Kioxia)
2nd Author's Name Akira Iwata  
2nd Author's Affiliation Kioxia Corporation (Kioxia)
3rd Author's Name Goichi Otomo  
3rd Author's Affiliation Kioxia Corporation (Kioxia)
4th Author's Name Tomoaki Suzuki  
4th Author's Affiliation Kioxia Corporation (Kioxia)
5th Author's Name Hiroaki Iijima  
5th Author's Affiliation Kioxia Corporation (Kioxia)
6th Author's Name Mikio Shiraishi  
6th Author's Affiliation Kioxia Corporation (Kioxia)
7th Author's Name Shinya Kawakami  
7th Author's Affiliation Kioxia Corporation (Kioxia)
8th Author's Name Masatomo Eimitsu  
8th Author's Affiliation Kioxia Corporation (Kioxia)
9th Author's Name Yoshiki Matsuoka  
9th Author's Affiliation Kioxia Corporation (Kioxia)
10th Author's Name Kiyohito Sato  
10th Author's Affiliation Kioxia Corporation (Kioxia)
11th Author's Name Shigehiro Tsuchiya  
11th Author's Affiliation Kioxia Corporation (Kioxia)
12th Author's Name Yoshinori Shigeta  
12th Author's Affiliation Kioxia Corporation (Kioxia)
13th Author's Name Takuma Aoyama  
13th Author's Affiliation Kioxia Corporation (Kioxia)
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Speaker Author-1 
Date Time 2024-04-12 13:50:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2024-14 
Volume (vol) vol.124 
Number (no) no.3 
Page p.43 
#Pages 1 
Date of Issue 2024-04-04 (ICD) 

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