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Paper Abstract and Keywords
Presentation 2024-08-08 16:45
X-Filling and Test Scheduling Methods for Concurrent Testing Using Optimistically/Pessimistically Structural Symbolic Simulation
Haruta Tokuta, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.) CPSY2024-25 DC2024-25 RECONF2024-25
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, with the increasing test cost of VLSIs, it has become important to reduce the number of test patterns. Design-for-testability methods at register transfer level have been proposed to reduce the number of test patterns. The methods aim to concurrently test hardware elements in a data-path by assigning logical values to don't-care values (Xs) in control signals supplied to the data-path when a controller transitions between states. The conventional method aims to reduce the number of test patterns by testing as many hardware elements as possible using as few state transitions as possible. In this paper, we focus on operational units, which are hardware elements that require a large number of test patterns, and propose a X-filling method that concurrently tests operational units with as many state transitions as possible. We also propose a test scheduling method that determines the number of test patterns to be generated at each state transition in order to minimize the estimated number of test patterns for data-paths from controllers with X-filling.
Keyword (in Japanese) (See Japanese page) 
(in English) control signals / X-filling / concurrent test / structural symbolic simulation / pseudo boolean optimization / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 149, DC2024-25, pp. 46-51, Aug. 2024.
Paper # DC2024-25 
Date of Issue 2024-07-31 (CPSY, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2024-25 DC2024-25 RECONF2024-25

Conference Information
Committee CPSY DC RECONF IPSJ-ARC  
Conference Date 2024-08-07 - 2024-08-09 
Place (in Japanese) (See Japanese page) 
Place (in English) Awagin Hall 
Topics (in Japanese) (See Japanese page) 
Topics (in English) SWoPP2024: Parallel, Distributed and Cooperative Processing Systems and Dependable Computing 
Paper Information
Registration To DC 
Conference Code 2024-08-CPSY-DC-RECONF-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) X-Filling and Test Scheduling Methods for Concurrent Testing Using Optimistically/Pessimistically Structural Symbolic Simulation 
Sub Title (in English)  
Keyword(1) control signals  
Keyword(2) X-filling  
Keyword(3) concurrent test  
Keyword(4) structural symbolic simulation  
Keyword(5) pseudo boolean optimization  
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Keyword(8)  
1st Author's Name Haruta Tokuta  
1st Author's Affiliation Nihon University (Nihon Univ.)
2nd Author's Name Toshinori Hosokawa  
2nd Author's Affiliation Nihon University (Nihon Univ.)
3rd Author's Name Masayoshi Yoshimura  
3rd Author's Affiliation Kyoto Sangyo University (Kyoto Sangyo Univ.)
4th Author's Name Masayuki Arai  
4th Author's Affiliation Nihon University (Nihon Univ.)
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Speaker Author-1 
Date Time 2024-08-08 16:45:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # CPSY2024-25, DC2024-25, RECONF2024-25 
Volume (vol) vol.124 
Number (no) no.148(CPSY), no.149(DC), no.150(RECONF) 
Page pp.46-51 
#Pages
Date of Issue 2024-07-31 (CPSY, DC, RECONF) 


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