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Paper Abstract and Keywords
Presentation 2024-08-09 18:15
A Framework for reducing power consumption of multi-FPGA clusters
Kensuke Iizuka (Keio Univ.), Hideharu Amano (The Univ. of Tokyo) CPSY2024-41 DC2024-41 RECONF2024-41
Abstract (in Japanese) (See Japanese page) 
(in English) FPGA clusters are expected to execute the time-critical applications as Multi-access Edge Computing (MEC) servers.
We can improve the performance by directly connecting multiple FPGAs.
However, the power consumption of the interconnect between FPGAs accounts for most of the that of the system.
We propose a novel framework that supports the design of FPGA clusters while reducing power consumption
by utilizing the methods and algorithms of previous studies,
such as allocating the applications to multiple FPGAs and the power estimation model.
The proposed framework can reduce the power consumption of unnecessary interconnects when designing the application on multiple FPGAs under the power limit.
It can also support to design the applications on multiple FPGAs, which is more complicated than the conventional FPGA design flow.
The proposed framework can reduce the power consumption of the entire system by up to 52% with executing the applications on multiple boards.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA cluster / Power reduction / Framework / Multi-access Edge Computing (MEC) / 5G / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 150, RECONF2024-41, pp. 141-146, Aug. 2024.
Paper # RECONF2024-41 
Date of Issue 2024-07-31 (CPSY, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2024-41 DC2024-41 RECONF2024-41

Conference Information
Committee CPSY DC RECONF IPSJ-ARC  
Conference Date 2024-08-07 - 2024-08-09 
Place (in Japanese) (See Japanese page) 
Place (in English) Awagin Hall 
Topics (in Japanese) (See Japanese page) 
Topics (in English) SWoPP2024: Parallel, Distributed and Cooperative Processing Systems and Dependable Computing 
Paper Information
Registration To RECONF 
Conference Code 2024-08-CPSY-DC-RECONF-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Framework for reducing power consumption of multi-FPGA clusters 
Sub Title (in English)  
Keyword(1) FPGA cluster  
Keyword(2) Power reduction  
Keyword(3) Framework  
Keyword(4) Multi-access Edge Computing (MEC)  
Keyword(5) 5G  
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1st Author's Name Kensuke Iizuka  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Hideharu Amano  
2nd Author's Affiliation The University of Tokyo (The Univ. of Tokyo)
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Speaker Author-1 
Date Time 2024-08-09 18:15:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # CPSY2024-41, DC2024-41, RECONF2024-41 
Volume (vol) vol.124 
Number (no) no.148(CPSY), no.149(DC), no.150(RECONF) 
Page pp.141-146 
#Pages 6 
Date of Issue 2024-07-31 (CPSY, DC, RECONF) 

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