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Paper Abstract and Keywords
Presentation 2024-11-12 16:25
Implementation and Evaluation of Arithmetic Masking to Mitigate Side-channel Attacks on Wavefront Array-based DNN Accelerator
Hirokatsu Yamasaki, Kota Yoshida, Yuta Fukuda, Takeshi Fujino (Ritsumeikan Univ) VLD2024-36 ICD2024-54 DC2024-58 RECONF2024-66
Abstract (in Japanese) (See Japanese page) 
(in English) Since training deep neural networks (DNNs) requires huge costs, trained models are important intellectual property. Therefore, it is necessary to keep the trained models secret. In particular, edge AIs, which perform DNNs' inference in local devices, are at risk of stealing DNN models via physical attacks because attackers can directly access the devices. Although encrypting model parameters is a basic countermeasure to these attacks, there is leakage via side-channel information during inference because they are decrypted before calculation. In this paper, we propose an arithmetic masking countermeasure to mitigate side-channel attacks against a wavefront array, one of the DNN accelerators. We expect to mask the intermediate state with random numbers by extending the matrix size by adding random numbers to the multiplicand and multiplier matrix. In the experiment, we performed correlation power analysis on the wavefront array with the countermeasure implemented on FPGA. As a result, we demonstrate that model parameter could not be identified even with 500,000 power consumption traces.
Keyword (in Japanese) (See Japanese page) 
(in English) Edge AI / Wavefront array / Correlation power analysis / / / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 250, RECONF2024-66, pp. 55-60, Nov. 2024.
Paper # RECONF2024-66 
Date of Issue 2024-11-05 (VLD, ICD, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2024-36 ICD2024-54 DC2024-58 RECONF2024-66

Conference Information
Committee VLD DC RECONF ICD IPSJ-SLDM  
Conference Date 2024-11-12 - 2024-11-14 
Place (in Japanese) (See Japanese page) 
Place (in English) COMPAL HALL 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2024 -New Field of VLSI Design- 
Paper Information
Registration To RECONF 
Conference Code 2024-11-VLD-DC-RECONF-ICD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation and Evaluation of Arithmetic Masking to Mitigate Side-channel Attacks on Wavefront Array-based DNN Accelerator 
Sub Title (in English)  
Keyword(1) Edge AI  
Keyword(2) Wavefront array  
Keyword(3) Correlation power analysis  
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1st Author's Name Hirokatsu Yamasaki  
1st Author's Affiliation Ritsumeikan University (Ritsumeikan Univ)
2nd Author's Name Kota Yoshida  
2nd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ)
3rd Author's Name Yuta Fukuda  
3rd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ)
4th Author's Name Takeshi Fujino  
4th Author's Affiliation Ritsumeikan University (Ritsumeikan Univ)
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Speaker Author-1 
Date Time 2024-11-12 16:25:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2024-36, ICD2024-54, DC2024-58, RECONF2024-66 
Volume (vol) vol.124 
Number (no) no.247(VLD), no.248(ICD), no.249(DC), no.250(RECONF) 
Page pp.55-60 
#Pages 6 
Date of Issue 2024-11-05 (VLD, ICD, DC, RECONF) 

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