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Paper Abstract and Keywords
Presentation 2024-11-12 16:00
On design of a delay testable circuit with an embedded arbiter PUF
Hayato Miki, Hiroyuki Yotsuyanagi (Tokushima Univ.), Masaki Hashizume (OUJ) VLD2024-39 ICD2024-57 DC2024-61 RECONF2024-69
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, the increase in counterfeit ICs has become one of the main threats to the reliability and security of electronic devices.
Physically Unclonable Function(PUF) has been proposed to improve the security and reliability of ICs.
PUF can generate unique values by utilizing manufacturing variations such as transistor thresholds and wiring parasitic capacitances and can identify individual chips.
However, the PUF circuit must be embedded to generate unique values, which increases the area overhead.
This paper proposes a new design of an arbiter PUF embedded in a design-for-testability circuit.
The delay elements in the delay testable circuit are also used for the arbiter PUF.
We implement the proposed circuit and evaluate the area overhead.
The simulation results confirmed that the response of the arbiter PUF is not predictable and depends on the device variations.
We also confirmed that the area overhead can be reduced compared to separately implementing an arbiter PUF.
Keyword (in Japanese) (See Japanese page) 
(in English) PUF(Physically Unclonable Function) / Design-for-Testability / individual identification / / / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 249, DC2024-61, pp. 73-78, Nov. 2024.
Paper # DC2024-61 
Date of Issue 2024-11-05 (VLD, ICD, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2024-39 ICD2024-57 DC2024-61 RECONF2024-69

Conference Information
Committee VLD DC RECONF ICD IPSJ-SLDM  
Conference Date 2024-11-12 - 2024-11-14 
Place (in Japanese) (See Japanese page) 
Place (in English) COMPAL HALL 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2024 -New Field of VLSI Design- 
Paper Information
Registration To DC 
Conference Code 2024-11-VLD-DC-RECONF-ICD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) On design of a delay testable circuit with an embedded arbiter PUF 
Sub Title (in English)  
Keyword(1) PUF(Physically Unclonable Function)  
Keyword(2) Design-for-Testability  
Keyword(3) individual identification  
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1st Author's Name Hayato Miki  
1st Author's Affiliation Tokushima University (Tokushima Univ.)
2nd Author's Name Hiroyuki Yotsuyanagi  
2nd Author's Affiliation Tokushima University (Tokushima Univ.)
3rd Author's Name Masaki Hashizume  
3rd Author's Affiliation The Open University of Japan (OUJ)
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Speaker Author-1 
Date Time 2024-11-12 16:00:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # VLD2024-39, ICD2024-57, DC2024-61, RECONF2024-69 
Volume (vol) vol.124 
Number (no) no.247(VLD), no.248(ICD), no.249(DC), no.250(RECONF) 
Page pp.73-78 
#Pages 6 
Date of Issue 2024-11-05 (VLD, ICD, DC, RECONF) 

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