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Paper Abstract and Keywords
Presentation 2024-11-14 09:25
Proposal for NV of Logic Cell Architecture for eFPGA IP
Keizo Hiraga (SSS), Kensu Seto, Masahiro Iida (Kumamoto Univ), Kazuhiro Bessho (SSS) VLD2024-63 ICD2024-81 DC2024-85 RECONF2024-93
Abstract (in Japanese) (See Japanese page) 
(in English) As eFPGAs (embedded FPGAs) are required to shift from hard IP to soft IP, we propose to make a new programmable logic cell architecture called PAE (Programmable AND element), which can replace LUT, non-volatile. It has been confirmed that PAE can reduce the configuration memory to about half of that of LUT with the same number of cells, thus achieving high implementation efficiency. Furthermore, by non-volatilizing the Configuration Logic Block (CLB) composed of PAEs using Non-Volatile Intellectual Property (NVIP), we expect to propose an eFPGA that achieves fast startup, low power consumption, high reliability and security.This is particularly promising for embedded systems and network equipments that, once installed, are hard to be accessed frequently. We propose a PAE-based CLB using a 40nm MTJ/CMOS hybrid process and a non-volatilization method using NVIP.
Keyword (in Japanese) (See Japanese page) 
(in English) eFPGA / PAE / NVFF / NVLatch / / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 250, RECONF2024-93, pp. 204-209, Nov. 2024.
Paper # RECONF2024-93 
Date of Issue 2024-11-05 (VLD, ICD, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2024-63 ICD2024-81 DC2024-85 RECONF2024-93

Conference Information
Committee VLD DC RECONF ICD IPSJ-SLDM  
Conference Date 2024-11-12 - 2024-11-14 
Place (in Japanese) (See Japanese page) 
Place (in English) COMPAL HALL 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2024 -New Field of VLSI Design- 
Paper Information
Registration To RECONF 
Conference Code 2024-11-VLD-DC-RECONF-ICD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Proposal for NV of Logic Cell Architecture for eFPGA IP 
Sub Title (in English)  
Keyword(1) eFPGA  
Keyword(2) PAE  
Keyword(3) NVFF  
Keyword(4) NVLatch  
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1st Author's Name Keizo Hiraga  
1st Author's Affiliation Sony Semiconductor Solutions Corporation (SSS)
2nd Author's Name Kensu Seto  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ)
3rd Author's Name Masahiro Iida  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ)
4th Author's Name Kazuhiro Bessho  
4th Author's Affiliation Sony Semiconductor Solutions Corporation (SSS)
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Speaker Author-1 
Date Time 2024-11-14 09:25:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2024-63, ICD2024-81, DC2024-85, RECONF2024-93 
Volume (vol) vol.124 
Number (no) no.247(VLD), no.248(ICD), no.249(DC), no.250(RECONF) 
Page pp.204-209 
#Pages 6 
Date of Issue 2024-11-05 (VLD, ICD, DC, RECONF) 

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