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Paper Abstract and Keywords
Presentation 2024-11-14 11:20
Impact of Size Effect on Delay Time of On-Chip Interconnects under Cryogenic Conditions
Tatsuya Ueda, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine (Univ Shiga Prefecture) VLD2024-70 ICD2024-88 DC2024-92 RECONF2024-100
Abstract (in Japanese) (See Japanese page) 
(in English) In a quantum computer, it is expected that the control function of qubits will be integrated into an integrated circuit and operated in cryogenic environment.
In general, as the temperature decreases, the wire resistance decreases , and the delay time also decreases accordingly.
At cryogenic environment, mean free path of electrons become longer.
The decrease in wire resistance becomes slower due to the size effect.
The signal propagation delay is contains the gate delay and interconnect delay.
If the wire resistance is sufficiently small, the gate delay is dominant.
However, under cryogenic condition, the size effect causes error in the estimation of interconnct delay.
It is not clear at what level of wire length the impact of size effect on interconnect delay becomes significant.
In this paper, we evaluate the wire length at which the influence of size effect on interconnect delay under cryogenic condition becomes non-negligible.
Compared to the case where wire resistance is based on the RRR, we found that there is a 10% error in delay time when the wiring length is 123 $mu$m, and there is an 80.7% error when the wiring length is 1000 $mu$m.
Keyword (in Japanese) (See Japanese page) 
(in English) Cryogenic / Size effect / delay / / / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 248, ICD2024-88, pp. 243-246, Nov. 2024.
Paper # ICD2024-88 
Date of Issue 2024-11-05 (VLD, ICD, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2024-70 ICD2024-88 DC2024-92 RECONF2024-100

Conference Information
Committee VLD DC RECONF ICD IPSJ-SLDM  
Conference Date 2024-11-12 - 2024-11-14 
Place (in Japanese) (See Japanese page) 
Place (in English) COMPAL HALL 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2024 -New Field of VLSI Design- 
Paper Information
Registration To ICD 
Conference Code 2024-11-VLD-DC-RECONF-ICD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Impact of Size Effect on Delay Time of On-Chip Interconnects under Cryogenic Conditions 
Sub Title (in English)  
Keyword(1) Cryogenic  
Keyword(2) Size effect  
Keyword(3) delay  
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1st Author's Name Tatsuya Ueda  
1st Author's Affiliation University of Shiga Prefecture (Univ Shiga Prefecture)
2nd Author's Name Akira Tsuchiya  
2nd Author's Affiliation University of Shiga Prefecture (Univ Shiga Prefecture)
3rd Author's Name Toshiyuki Inoue  
3rd Author's Affiliation University of Shiga Prefecture (Univ Shiga Prefecture)
4th Author's Name Keiji Kishine  
4th Author's Affiliation University of Shiga Prefecture (Univ Shiga Prefecture)
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Speaker Author-1 
Date Time 2024-11-14 11:20:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # VLD2024-70, ICD2024-88, DC2024-92, RECONF2024-100 
Volume (vol) vol.124 
Number (no) no.247(VLD), no.248(ICD), no.249(DC), no.250(RECONF) 
Page pp.243-246 
#Pages 4 
Date of Issue 2024-11-05 (VLD, ICD, DC, RECONF) 

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