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| Presentation | 2025-01-16 09:50 Implementation of an Error Correcting Decoder for Surface Code Using Greedy Algorithm on ASIC by RTL and Behavioral Synthesis Ren Aoyama (KIT), Junichiro Kaodomoto (UTokyo), Kazutoshi Kobayashi (KIT)  VLD2024-78 RECONF2024-108 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Quantum computers are expected to address the limitations of performance improvement due to the miniaturization of classical computers. Error correction is mandatory for quantum computers to perform practical computations. Surface code is one of the representative error correction methods, offering high error tolerance. In this study, we designed an error correction decoder, which is a part of the error correction functionality, using C++. The decoder employs the Iterative Greedy algorithm, one of greedy algorithm. The developed design was synthesized into HDL to evaluate the area. The results were compared with previous research that used HDL for design. The comparison revealed a reduction in area by 22.0%. Additionally, logic synthesis targeting an FPGA was performed, and a comparison of the utilized resources showed that LUTs and FFs were 4.39%and 29.3%, respectively, compared to the previous study. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Quantum Computer / Surface Code / Decoder / Greedy Algorithm / Error Correction / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 124, no. 329, VLD2024-78, pp. 13-17, Jan. 2025. | |
| Paper # | VLD2024-78 | |
| Date of Issue | 2025-01-09 (VLD, RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2024-78 RECONF2024-108 |
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| Conference Information | |
| Committee | VLD RECONF |
| Conference Date | 2025-01-16 - 2025-01-17 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Yokohama Technology Campus Flagship Building |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2025-01-VLD-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of an Error Correcting Decoder for Surface Code Using Greedy Algorithm on ASIC by RTL and Behavioral Synthesis |
| Sub Title (in English) | |
| Keyword(1) | Quantum Computer |
| Keyword(2) | Surface Code |
| Keyword(3) | Decoder |
| Keyword(4) | Greedy Algorithm |
| Keyword(5) | Error Correction |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Ren Aoyama |
| 1st Author's Affiliation | Kyoto Institute of Technology (KIT) |
| 2nd Author's Name | Junichiro Kaodomoto |
| 2nd Author's Affiliation | The University of Tokyo (UTokyo) |
| 3rd Author's Name | Kazutoshi Kobayashi |
| 3rd Author's Affiliation | Kyoto Institute of Technology (KIT) |
| 4th Author's Name | |
| 4th Author's Affiliation | () |
| 5th Author's Name | |
| 5th Author's Affiliation | () |
| 6th Author's Name | |
| 6th Author's Affiliation | () |
| Speaker | Author-1 |
| Date Time | 2025-01-16 09:50:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2024-78, RECONF2024-108 |
| Volume (vol) | vol.124 |
| Number (no) | no.329(VLD), no.330(RECONF) |
| Page | pp.13-17 |
| #Pages | 5 |
| Date of Issue | 2025-01-09 (VLD, RECONF) |
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