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Paper Abstract and Keywords
Presentation 2025-01-17 15:10
Proposal of Heterogeneous Structure Clusters Using PAE Cells for eFPGA IP
Tatsuya Sasaki, Ryo Iwasaki, Kensyu Seto, Masahiro Iida (Kumamoto Univ.) VLD2024-98 RECONF2024-128
Abstract (in Japanese) (See Japanese page) 
(in English) We are currently proposing a new logic cell called the PAE Cell as a replacement for LUTs (Look-Up Tables) in eFPGA IP. The PAE Cell achieves equivalent logic representation capabilities to LUTs while requiring less configuration memory. However, its effectiveness is significantly reduced when used with conventional cluster structures and interconnect architectures. In this study, we propose a heterogeneous cluster structure that uses PAE Cells with varying input counts as logic cells, aiming to reduce the number of clusters and optimize wiring within clusters. Experimental results show that this
heterogeneous cluster structure is not efficiently packed by VPR’s packing algorithm, leading to an increase in the number of clusters compared to the ideal case. Therefore, it has been concluded that a packing algorithm tailored to the proposed cluster structure is necessary to efficiently utilize it.
Keyword (in Japanese) (See Japanese page) 
(in English) eFPGA IP / PAECell / Technology mapping / Heterogeneous structure cluster / / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 330, RECONF2024-128, pp. 122-127, Jan. 2025.
Paper # RECONF2024-128 
Date of Issue 2025-01-09 (VLD, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2024-98 RECONF2024-128

Conference Information
Committee VLD RECONF  
Conference Date 2025-01-16 - 2025-01-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Yokohama Technology Campus Flagship Building 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To RECONF 
Conference Code 2025-01-VLD-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Proposal of Heterogeneous Structure Clusters Using PAE Cells for eFPGA IP 
Sub Title (in English)  
Keyword(1) eFPGA IP  
Keyword(2) PAECell  
Keyword(3) Technology mapping  
Keyword(4) Heterogeneous structure cluster  
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1st Author's Name Tatsuya Sasaki  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Ryo Iwasaki  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Kensyu Seto  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Masahiro Iida  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Speaker Author-1 
Date Time 2025-01-17 15:10:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2024-98, RECONF2024-128 
Volume (vol) vol.124 
Number (no) no.329(VLD), no.330(RECONF) 
Page pp.122-127 
#Pages 6 
Date of Issue 2025-01-09 (VLD, RECONF) 

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