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Paper Abstract and Keywords
Presentation 2025-08-05 16:25
A Graph Matching-Based Technology Mapping Method for Multi-Output Logic Cell PAE
Ryo Iwasaki, Souta Kohata, Kenshu Seto, Masahiro Iida (Kumamoto Univ.) CPSY2025-46 DC2025-46 RECONF2025-46
Abstract (in Japanese) (See Japanese page) 
(in English) eFPGAs, which can be embedded in SoCs and ASICs, face the challenge of increasing area with the growing number of configuration memories. To address this issue, the PAE (Programmable-as-an-Element) Cell has been proposed as a new logic cell. Compared to conventional LUT-based logic cells, the PAE Cell is characterized by having fewer configuration memories and multiple outputs. This is expected to improve area efficiency in terms of both memory size and the number of logic cells. wever, existing technology mapping methods for multi-output logic cells have issues, particularly in fully leveraging the effectiveness of the PAE Cell, which cannot be ignored. Therefore, this paper proposes a graph-matching-based technology mapping method that focuses on the internal structure of the PAE Cell. In this work, we propose two methods: an area-priority method and a delay-priority (depth-priority) method. The evaluation results show that the number of cells was reduced by 36.2% and the number of configuration memories was reduced by 67.9% compared to the conventional 4-LUT. Furthermore, a comparison of the two methods confirmed a previously un-evaluated trade-off between area and depth.
Keyword (in Japanese) (See Japanese page) 
(in English) Technology Mapping / PAE Cell / PA circuit / / / / /  
Reference Info. IEICE Tech. Rep., vol. 125, no. 144, RECONF2025-46, pp. 128-133, Aug. 2025.
Paper # RECONF2025-46 
Date of Issue 2025-07-28 (CPSY, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2025-46 DC2025-46 RECONF2025-46

Conference Information
Committee CPSY DC RECONF IPSJ-ARC  
Conference Date 2025-08-04 - 2025-08-06 
Place (in Japanese) (See Japanese page) 
Place (in English) Sunport Hall Takamatsu 
Topics (in Japanese) (See Japanese page) 
Topics (in English) SWoPP2025: Parallel, Distributed and Cooperative Processing Systems and Dependable Computing 
Paper Information
Registration To RECONF 
Conference Code 2025-08-CPSY-DC-RECONF-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Graph Matching-Based Technology Mapping Method for Multi-Output Logic Cell PAE 
Sub Title (in English)  
Keyword(1) Technology Mapping  
Keyword(2) PAE Cell  
Keyword(3) PA circuit  
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1st Author's Name Ryo Iwasaki  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Souta Kohata  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Kenshu Seto  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Masahiro Iida  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Speaker Author-1 
Date Time 2025-08-05 16:25:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # CPSY2025-46, DC2025-46, RECONF2025-46 
Volume (vol) vol.125 
Number (no) no.142(CPSY), no.143(DC), no.144(RECONF) 
Page pp.128-133 
#Pages 6 
Date of Issue 2025-07-28 (CPSY, DC, RECONF) 

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