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Paper Abstract and Keywords
Presentation 2025-10-18 16:40
Implementation of Ultra-Low Power Spiking Neural Network Circuits Using High-Threshold Voltage MOSFETs and its Classification Tasks Application
Tetsuta Sakai, Satoshi Moriya, Kyotaro Gotsu, Hideaki Yamamoto, Shigeo Sato (Tohoku Univ.) NC2025-30
Abstract (in Japanese) (See Japanese page) 
(in English) With the growing sophistication of AI-based information processing, reducing power consumption and lowering training costs have become major challenges. At the edge of networks, where circuit area and power budgets are highly constrained, the development of dedicated edge devices is essential. In this study, we target the development of such low-power edge devices by implementing an analog spiking neural network (SNN) circuit and applying it to classification tasks. The circuit consists of 256 neuron circuits and synapse circuits connecting them. By operating high-threshold MOSFETs in the subthreshold region, we achieved ultra-low-power operation. For reservoir computing applications, we further introduced a notion of virtual distance into the network and applied distance-dependent synaptic weights. This increased the variance in connection degrees and improved separability. The designed analog SNN circuit was fabricated using a 65 nm CMOS process and employed as a reservoir layer for classification of the DVS Gesture dataset, which consists of event-based gesture data. Spike outputs from the circuit were used to train a readout layer with ridge regression. As a result, we achieved over 70% accuracy in 8-class classification with only 1.44 nW/inference. Compared with conventional digital implementations, this represents less than 1/100 energy consumption. These results demonstrate the potential of analog SNN circuits for edge applications.
Keyword (in Japanese) (See Japanese page) 
(in English) Spiking Neuron / Analog CMOS Circuit / Edge Computing / Time-series Signal Classification / / / /  
Reference Info. IEICE Tech. Rep., vol. 125, no. 205, NC2025-30, pp. 35-35, Oct. 2025.
Paper # NC2025-30 
Date of Issue 2025-10-11 (NC) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF NC2025-30

Conference Information
Committee NC MBE  
Conference Date 2025-10-18 - 2025-10-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Tohoku University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) NC, ME, etc. 
Paper Information
Registration To NC 
Conference Code 2025-10-NC-MBE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation of Ultra-Low Power Spiking Neural Network Circuits Using High-Threshold Voltage MOSFETs and its Classification Tasks Application 
Sub Title (in English)  
Keyword(1) Spiking Neuron  
Keyword(2) Analog CMOS Circuit  
Keyword(3) Edge Computing  
Keyword(4) Time-series Signal Classification  
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1st Author's Name Tetsuta Sakai  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Satoshi Moriya  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
3rd Author's Name Kyotaro Gotsu  
3rd Author's Affiliation Tohoku University (Tohoku Univ.)
4th Author's Name Hideaki Yamamoto  
4th Author's Affiliation Tohoku University (Tohoku Univ.)
5th Author's Name Shigeo Sato  
5th Author's Affiliation Tohoku University (Tohoku Univ.)
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Speaker Author-1 
Date Time 2025-10-18 16:40:00 
Presentation Time 25 minutes 
Registration for NC 
Paper # NC2025-30 
Volume (vol) vol.125 
Number (no) no.205 
Page p.35 
#Pages 1 
Date of Issue 2025-10-11 (NC) 

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