| Paper Abstract and Keywords |
| Presentation |
2025-11-14 16:40
Evaluation of digital circuit characteristic variations caused by intentional backside voltage application in flip-chip devices Shuhei Yokota, Rikuu Hasegawa, Takuya Wadatsumi, Kazuki Monta (Kobe Univ.), Junichi Sakamoto, Shinichi Kawamura (AIST), Makoto Nagata (Kobe Univ.) HWS2025-70 ICD2025-35 |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
In recent years, flip-chip packaging, a technique in which IC chips are flipped and directly mounted onto the
substrate, has become the mainstream approach. While flip-chip implementation offers the advantage of achieving higher
integration density, it also has the potential drawback that the exposed backside of the Si chip is susceptible to various disturbance.
In this study, we explore the effects of backside disturbances in a cascaded inverter structure and exploit several techniques to
evaluate the variation of digital circuit characteristics . |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Cascaded inverter / Flip-chip / Backside biasing / / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 125, no. 249, ICD2025-35, pp. 45-47, Nov. 2025. |
| Paper # |
ICD2025-35 |
| Date of Issue |
2025-11-07 (HWS, ICD) |
| ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Download PDF |
HWS2025-70 ICD2025-35 |
| Conference Information |
| Committee |
ICD HWS |
| Conference Date |
2025-11-14 - 2025-11-14 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Kumamoto University |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
Hardware Security, etc. |
| Paper Information |
| Registration To |
ICD |
| Conference Code |
2025-11-ICD-HWS |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Evaluation of digital circuit characteristic variations caused by intentional backside voltage application in flip-chip devices |
| Sub Title (in English) |
|
| Keyword(1) |
Cascaded inverter |
| Keyword(2) |
Flip-chip |
| Keyword(3) |
Backside biasing |
| Keyword(4) |
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| 1st Author's Name |
Shuhei Yokota |
| 1st Author's Affiliation |
Kobe University (Kobe Univ.) |
| 2nd Author's Name |
Rikuu Hasegawa |
| 2nd Author's Affiliation |
Kobe University (Kobe Univ.) |
| 3rd Author's Name |
Takuya Wadatsumi |
| 3rd Author's Affiliation |
Kobe University (Kobe Univ.) |
| 4th Author's Name |
Kazuki Monta |
| 4th Author's Affiliation |
Kobe University (Kobe Univ.) |
| 5th Author's Name |
Junichi Sakamoto |
| 5th Author's Affiliation |
National Institute of Advanced Industrial Science and Technology (AIST) |
| 6th Author's Name |
Shinichi Kawamura |
| 6th Author's Affiliation |
National Institute of Advanced Industrial Science and Technology (AIST) |
| 7th Author's Name |
Makoto Nagata |
| 7th Author's Affiliation |
Kobe University (Kobe Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2025-11-14 16:40:00 |
| Presentation Time |
25 minutes |
| Registration for |
ICD |
| Paper # |
HWS2025-70, ICD2025-35 |
| Volume (vol) |
vol.125 |
| Number (no) |
no.248(HWS), no.249(ICD) |
| Page |
pp.45-47 |
| #Pages |
3 |
| Date of Issue |
2025-11-07 (HWS, ICD) |