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Paper Abstract and Keywords
Presentation 2025-12-05 14:50
Variable-Clock Controlled TDC for Path Delay Measurement on FPGA
Seito Takahashi, Satoshi Ohtake (Oita Univ.) DC2025-104
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose a tapped delay line (TDL) based time-to-digital converter (TDC) with variable clock control for accurately measuring path delays with different slack values on FPGAs.By using the dynamic phase shift (DPS) function of an on-chip PLL, the phase of a high-frequency clock can be finely adjusted, enabling flexible placement of the measurement window and reducing the required carry-chain length.Furthermore, a dedicated glitch-free clock-switching IP is employed to supply a low-skew clock without passing through synthesized logic, improving TDC stability.Experiments on an Intel Cyclone V FPGA showed that the proposed variable-clock-controlled TDC can clearly distinguish the delay differences among 16 paths, confirming its effectiveness for path-delay measurement on FPGAs.
Keyword (in Japanese) (See Japanese page) 
(in English) Time-to-digital converter / FPGA / transition fault / silicon lifecycle management / / / /  
Reference Info. IEICE Tech. Rep., vol. 125, no. 278, DC2025-104, pp. 18-23, Dec. 2025.
Paper # DC2025-104 
Date of Issue 2025-11-28 (DC) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF DC2025-104

Conference Information
Committee DC  
Conference Date 2025-12-05 - 2025-12-05 
Place (in Japanese) (See Japanese page) 
Place (in English) Kokubu Park Plaza 2F conference room 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Winter Workshop on Safety 
Paper Information
Registration To DC 
Conference Code 2025-12-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Variable-Clock Controlled TDC for Path Delay Measurement on FPGA 
Sub Title (in English)  
Keyword(1) Time-to-digital converter  
Keyword(2) FPGA  
Keyword(3) transition fault  
Keyword(4) silicon lifecycle management  
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1st Author's Name Seito Takahashi  
1st Author's Affiliation Oita University (Oita Univ.)
2nd Author's Name Satoshi Ohtake  
2nd Author's Affiliation Oita University (Oita Univ.)
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Speaker Author-1 
Date Time 2025-12-05 14:50:00 
Presentation Time 20 minutes 
Registration for DC 
Paper # DC2025-104 
Volume (vol) vol.125 
Number (no) no.278 
Page pp.18-23 
#Pages 6 
Date of Issue 2025-11-28 (DC) 

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