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Paper Abstract and Keywords
Presentation 2026-01-27 15:00
Design and Implementation of a Verilog HDL Compiler to Accelerate RTL Simulation
Lennart Trunk, Yuki Yagi, Kenji Kise (Science Tokyo) VLD2025-69 RECONF2025-120
Abstract (in Japanese) (See Japanese page) 
(in English) Verilog HDL is a widely adopted hardware description language for the design and simulation of register-transfer level (RTL) circuits. However, large-scale RTL simulation requires an immense amount of time, often acting as a bottleneck in the development cycle. The primary goal of this research is to accelerate simulation of RTL circuits designed using Verilog HDL.
The result of this is the VCC compiler, which compiles a subset of Verilog HDL into C++. We demonstrate that restrictions to a subset of Verilog HDL and compile-time optimizations of VCC significantly reduce scheduling overhead and achieve significant RTL simulation acceleration. The evaluation compares VCC against Verilator, a widely used open-source simulator for Verilog HDL, in two environments and across three benchmarks that were designed in Verilog HDL and adjusted to fit VCC's limitations. In all benchmarks and environments, VCC demonstrated a higher simulation speed compared to Verilator.
Keyword (in Japanese) (See Japanese page) 
(in English) VCC / Verilog HDL / RTL Simulation / C++ Compilation / Compiler Optimization / Verilator / /  
Reference Info. IEICE Tech. Rep., vol. 125, no. 342, RECONF2025-120, pp. 12-17, Jan. 2026.
Paper # RECONF2025-120 
Date of Issue 2026-01-20 (VLD, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2025-69 RECONF2025-120

Conference Information
Committee RECONF VLD  
Conference Date 2026-01-27 - 2026-01-28 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To RECONF 
Conference Code 2026-01-RECONF-VLD 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design and Implementation of a Verilog HDL Compiler to Accelerate RTL Simulation 
Sub Title (in English)  
Keyword(1) VCC  
Keyword(2) Verilog HDL  
Keyword(3) RTL Simulation  
Keyword(4) C++ Compilation  
Keyword(5) Compiler Optimization  
Keyword(6) Verilator  
Keyword(7)  
Keyword(8)  
1st Author's Name Lennart Trunk  
1st Author's Affiliation Institute of Science Tokyo (Science Tokyo)
2nd Author's Name Yuki Yagi  
2nd Author's Affiliation Institute of Science Tokyo (Science Tokyo)
3rd Author's Name Kenji Kise  
3rd Author's Affiliation Institute of Science Tokyo (Science Tokyo)
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Speaker Author-1 
Date Time 2026-01-27 15:00:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2025-69, RECONF2025-120 
Volume (vol) vol.125 
Number (no) no.341(VLD), no.342(RECONF) 
Page pp.12-17 
#Pages 6 
Date of Issue 2026-01-20 (VLD, RECONF) 

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