Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2026-01-28 10:50
FPGA-Based Design of Multi-Precision Floating-Point Arithmetic Units for Image Recognition Applications
Hiroki Kurihara, Fumiya Kono (SIST) VLD2025-73 RECONF2025-124
Abstract (in Japanese) (See Japanese page) 
(in English) INT8 quantization is widely used in FPGA-based deep neural network inference to reduce circuit area and memory usage; however, it may degrade inference accuracy.

In this work, we design low-bit-width floating-point arithmetic units whose exponent and mantissa bit widths are configurable at synthesis time, and implement a YOLOv3 tiny inference accelerator on an FPGA. We evaluate the trade-offs between numerical precision, circuit area, and inference latency, and discuss the feasibility of low-bit-width floating-point arithmetic as an alternative to INT8 quantization.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Object Detection / YOLOv3 tiny / Floating-Point Arithmetic / Variable Precision / Inference Accelerator / /  
Reference Info. IEICE Tech. Rep., vol. 125, no. 342, RECONF2025-124, pp. 33-38, Jan. 2026.
Paper # RECONF2025-124 
Date of Issue 2026-01-20 (VLD, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2025-73 RECONF2025-124

Conference Information
Committee RECONF VLD  
Conference Date 2026-01-27 - 2026-01-28 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To RECONF 
Conference Code 2026-01-RECONF-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) FPGA-Based Design of Multi-Precision Floating-Point Arithmetic Units for Image Recognition Applications 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Object Detection  
Keyword(3) YOLOv3 tiny  
Keyword(4) Floating-Point Arithmetic  
Keyword(5) Variable Precision  
Keyword(6) Inference Accelerator  
Keyword(7)  
Keyword(8)  
1st Author's Name Hiroki Kurihara  
1st Author's Affiliation Shizuoka Institute of Science and Technology (SIST)
2nd Author's Name Fumiya Kono  
2nd Author's Affiliation Shizuoka Institute of Science and Technology (SIST)
3rd Author's Name  
3rd Author's Affiliation ()
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2026-01-28 10:50:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2025-73, RECONF2025-124 
Volume (vol) vol.125 
Number (no) no.341(VLD), no.342(RECONF) 
Page pp.33-38 
#Pages 6 
Date of Issue 2026-01-20 (VLD, RECONF) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan