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Paper Abstract and Keywords
Presentation 2026-02-17 16:00
A study on countermeasures against degradation of CMOS circuits
Haruka Sakai, Yukiya Miura (Tokyo Metropolitan Univ.) DC2025-122
Abstract (in Japanese) (See Japanese page) 
(in English) As integrated circuits continue to scale, reliability degradation caused by aging effects such as NBTI, PBTI, and CHC has become a critical issue. Transistor degradation increases propagation delay, which can lead to timing failures in synchronous circuits. This study investigates a mitigation technique using Driving Strength Controlled Transistor (DSCT), which dynamically adjust transistor channel width during operation to enhance gate driving strength. By increasing the drain current, DSCT compensates for delay degradation caused by aging. The effectiveness of the proposed approach at gate circuits is evaluated through circuit-level simulations.
Keyword (in Japanese) (See Japanese page) 
(in English) DSCT / Integrated Circuits / Aging Degradation / Propagation Delay / Reliability Enhancement / / /  
Reference Info. IEICE Tech. Rep., vol. 125, no. 352, DC2025-122, pp. 65-70, Feb. 2026.
Paper # DC2025-122 
Date of Issue 2026-02-10 (DC) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF DC2025-122

Conference Information
Committee DC  
Conference Date 2026-02-17 - 2026-02-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2026-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A study on countermeasures against degradation of CMOS circuits 
Sub Title (in English)  
Keyword(1) DSCT  
Keyword(2) Integrated Circuits  
Keyword(3) Aging Degradation  
Keyword(4) Propagation Delay  
Keyword(5) Reliability Enhancement  
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Keyword(7)  
Keyword(8)  
1st Author's Name Haruka Sakai  
1st Author's Affiliation Tokyo Metropolitan University (Tokyo Metropolitan Univ.)
2nd Author's Name Yukiya Miura  
2nd Author's Affiliation Tokyo Metropolitan University (Tokyo Metropolitan Univ.)
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Speaker Author-1 
Date Time 2026-02-17 16:00:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2025-122 
Volume (vol) vol.125 
Number (no) no.352 
Page pp.65-70 
#Pages 6 
Date of Issue 2026-02-10 (DC) 

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