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Paper Abstract and Keywords
Presentation 2026-02-19 17:15
FPGA-based End-to-End Learned Image Compression Prototype
Jing Wang, Heming Sun (YNU) ITS2025-61 IE2025-76
Abstract (in Japanese) (See Japanese page) 
(in English) This report describes an FPGA-based end-to-end learned image compression (LIC) prototype that continuously captures live video, compresses it on an encoder SoC-FPGA board (ZCU102), streams the compressed representation over Ethernet, and reconstructs and displays the video on a decoder SoC-FPGA board (ZC706). On the encoder, 640 ×480 frames are captured from a USB webcam using OpenCV on PYNQ, processed by a custom PL analysis-transform IP, and entropy-coded on the PS using rANS before TCP transmission. On the decoder, the PS performs rANS decoding on PetaLinux, a custom PL synthesis (inverse) transform IP reconstructs frames, and an HDMI output chain is driven through VDMA and standard video-out IP. We instrument encoder-side stage boundaries with monotonic timestamps and additionally estimate end-to-end latency using an on-screen visual timestamp reference. A throughput of 3.18 fps for the current 98-DSP transform IP with an effective transform input of 512 ×640, derived from raw 640 ×480 camera frames was measured, together with an encoder-side latency breakdown
that exposes current bottlenecks. Power logging via on-board Linux hwmon rails is implemented and time-aligned with the pipeline. Finally, we discuss bottlenecks suggested by the current architecture—PS–PL data movement, CPU-side rANS cost, and limited inter-stage overlap.
Keyword (in Japanese) (See Japanese page) 
(in English) learned image compression / FPGA-SoC / PYNQ / PetaLinux / / / /  
Reference Info. IEICE Tech. Rep., vol. 125, no. 356, IE2025-76, pp. 124-128, Feb. 2026.
Paper # IE2025-76 
Date of Issue 2026-02-12 (ITS, IE) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ITS2025-61 IE2025-76

Conference Information
Committee IE ITS ITE-MMS ITE-ME ITE-AIT ITE-SIP  
Conference Date 2026-02-19 - 2026-02-20 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To IE 
Conference Code 2026-02-IE-ITS-MMS-ME-AIT-SIP 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) FPGA-based End-to-End Learned Image Compression Prototype 
Sub Title (in English)  
Keyword(1) learned image compression  
Keyword(2) FPGA-SoC  
Keyword(3) PYNQ  
Keyword(4) PetaLinux  
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1st Author's Name Jing Wang  
1st Author's Affiliation Yokohama National University (YNU)
2nd Author's Name Heming Sun  
2nd Author's Affiliation Yokohama National University (YNU)
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Speaker Author-1 
Date Time 2026-02-19 17:15:00 
Presentation Time 15 minutes 
Registration for IE 
Paper # ITS2025-61, IE2025-76 
Volume (vol) vol.125 
Number (no) no.355(ITS), no.356(IE) 
Page pp.124-128 
#Pages 5 
Date of Issue 2026-02-12 (ITS, IE) 

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