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Paper Abstract and Keywords
Presentation 2026-03-06 14:15
Automation of the Digital Design Flow for the Agile-Chip Platform
Hideharu Amano, Atsutake Kosuge, Naonobu Shimamoto, Tohru Mogami, Hirofumi Sumi, Yurie Inoue, Makoto Ikeda, Yosiro Mita (Tokyo Univ.) VLD2025-108 HWS2025-104 ICD2025-119
Abstract (in Japanese) (See Japanese page) 
(in English) Because ASIC design and fabrication require substantial cost and long lead times, they are not well suited to student
laboratory courses. To address this issue, we proposed a student experiment that can be completed rapidly and at low cost by
using a short-turn, low-cost Structured-ASIC design and fabrication approach that we call the Agile-Chip Platform, and we
piloted an exercise in which students design and fabricate a simple ring oscillator. This experiment can be carried out with
relatively little knowledge of electronic circuits and enables students to easily experience chip implementation; however, it
remains far from the full design process of a practical digital IC. In this report, we describe an experiment in which we used the
Agile-Chip Platform to implement digital logic circuits on a gate array, connect them to an embedded RISC-V CPU, and build
a small-scale system-on-a-chip (SoC) that can be powered on and functionally verified. The circuits implemented on the gate
array can be designed using a standard flow―from HDL description, through logic synthesis, to automatic layout. Because
the current Agile-Chip Platform performs interconnect wiring using only five metal layers, some challenges arise during the
automatic routing stage; however, these can be automatically resolved using TCL scripts. In a trial conducted in August 2025,
six participants independently designed and implemented their own circuits within three days. Two weeks later, the packaged
chips were evaluated on a dedicated debug board, and five different chips were confirmed to operate as designed.
Keyword (in Japanese) (See Japanese page) 
(in English) Student Lab for beginners of Semiconductor education / Minimal Fab. / Agile design / / / / /  
Reference Info. IEICE Tech. Rep., vol. 125, no. 382, VLD2025-108, pp. 181-186, March 2026.
Paper # VLD2025-108 
Date of Issue 2026-02-25 (VLD, HWS, ICD) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2025-108 HWS2025-104 ICD2025-119

Conference Information
Committee ICD HWS VLD  
Conference Date 2026-03-04 - 2026-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2026-03-ICD-HWS-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Automation of the Digital Design Flow for the Agile-Chip Platform 
Sub Title (in English)  
Keyword(1) Student Lab for beginners of Semiconductor education  
Keyword(2) Minimal Fab.  
Keyword(3) Agile design  
Keyword(4)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Hideharu Amano  
1st Author's Affiliation The University of Tokyo (Tokyo Univ.)
2nd Author's Name Atsutake Kosuge  
2nd Author's Affiliation The University of Tokyo (Tokyo Univ.)
3rd Author's Name Naonobu Shimamoto  
3rd Author's Affiliation The University of Tokyo (Tokyo Univ.)
4th Author's Name Tohru Mogami  
4th Author's Affiliation The University of Tokyo (Tokyo Univ.)
5th Author's Name Hirofumi Sumi  
5th Author's Affiliation The University of Tokyo (Tokyo Univ.)
6th Author's Name Yurie Inoue  
6th Author's Affiliation The University of Tokyo (Tokyo Univ.)
7th Author's Name Makoto Ikeda  
7th Author's Affiliation The University of Tokyo (Tokyo Univ.)
8th Author's Name Yosiro Mita  
8th Author's Affiliation The University of Tokyo (Tokyo Univ.)
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Speaker Author-1 
Date Time 2026-03-06 14:15:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2025-108, HWS2025-104, ICD2025-119 
Volume (vol) vol.125 
Number (no) no.382(VLD), no.383(HWS), no.384(ICD) 
Page pp.181-186 
#Pages 6 
Date of Issue 2026-02-25 (VLD, HWS, ICD) 

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