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Paper Abstract and Keywords
Presentation 2026-03-06 13:25
Design of In-Switch Rule Caching for a UPF Node with a P4 Switch and a Server
Naoki Wakami, Yutaro Yoshinaka, Junji Takemasa, Yuki Koizumi (UOsaka), Toru Hasegawa (Shimane Univ.) NS2025-323
Abstract (in Japanese) (See Japanese page) 
(in English) A User Plane Function (UPF) that can process millions of flows at terabit-class throughput is essential to satisfy 5G performance requirements. Programmable switches can achieve high throughput, but cannot accommodate a large number of flows due to its small memory capacity. To overcome this constraint, the authors are developing the hybrid UPF node, where the switch caches and processes only a small set of active flows, and CPU servers hold all the flows. We have identifies that frequent rule replacements make control plane CPUs bottleneck at the switch. Realizing rule caches fully on switch ASIC is promising; however, the ASIC inherent constraints of feed forward pipeline-based memory accesses and memory width make this design challenging. In this paper, we design a rule cache system fully operating on the switch ASIC, through appropriate function splitting in switch and server. We finally implement the prototype UPF node with a Tofino switch and CPU server running GPP-compliant 5G core software, and discuss the feasibility of terabit-class throughput.
Keyword (in Japanese) (See Japanese page) 
(in English) 5G / User plane function (UPF) / Programmable switch / CPU server / / / /  
Reference Info. IEICE Tech. Rep., vol. 125, no. 385, NS2025-323, pp. 597-602, March 2026.
Paper # NS2025-323 
Date of Issue 2026-02-25 (NS) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF NS2025-323

Conference Information
Committee IN NS  
Conference Date 2026-03-04 - 2026-03-06 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa-Ken Shichoson Jichi Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) General 
Paper Information
Registration To NS 
Conference Code 2026-03-IN-NS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design of In-Switch Rule Caching for a UPF Node with a P4 Switch and a Server 
Sub Title (in English)  
Keyword(1) 5G  
Keyword(2) User plane function (UPF)  
Keyword(3) Programmable switch  
Keyword(4) CPU server  
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1st Author's Name Naoki Wakami  
1st Author's Affiliation The University of Osaka (UOsaka)
2nd Author's Name Yutaro Yoshinaka  
2nd Author's Affiliation The University of Osaka (UOsaka)
3rd Author's Name Junji Takemasa  
3rd Author's Affiliation The University of Osaka (UOsaka)
4th Author's Name Yuki Koizumi  
4th Author's Affiliation The University of Osaka (UOsaka)
5th Author's Name Toru Hasegawa  
5th Author's Affiliation Shimane University (Shimane Univ.)
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Speaker Author-1 
Date Time 2026-03-06 13:25:00 
Presentation Time 25 minutes 
Registration for NS 
Paper # NS2025-323 
Volume (vol) vol.125 
Number (no) no.385 
Page pp.597-602 
#Pages 6 
Date of Issue 2026-02-25 (NS) 

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