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Paper Abstract and Keywords
Presentation 2026-03-07 11:25
A Study on Low-Latency Hardware for Post-Quantum Signature QR-UOV
Renma Sugai, Hiroshi Amagasa (Tohoku Univ.), Rei Ueno (Kyoto Univ.), Naofumi Homma (Tohoku Univ.) VLD2025-118 HWS2025-114 ICD2025-129
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes a low-latency hardware architecture for QR-UOV, a post-quantum signature scheme. QR-UOV is based on Multivariate Quadratic (MQ) cryptography and is currently selected as one of the 14 second-round candidates in the NIST Post-Quantum Cryptography (PQC) Standardization Process. To achieve high-speed operation, the proposed hardware utilizes a systolic array to parallelize the polynomial matrix-vector multiplications involved in key generation, signature generation, and verification. We implemented the proposed architecture on an FPGA and evaluated its performance in terms of latency and resource utilization. Experimental results demonstrate that the proposed QR-UOV hardware, configured with a $6 times 6$ systolic array, achieves a $34.4times$ speedup in key generation compared to a reference implementation using High-Level Synthesis (HLS).
Keyword (in Japanese) (See Japanese page) 
(in English) Post-Quantum Cryptography / Digital Signature / FPGA / QR-UOV / / / /  
Reference Info. IEICE Tech. Rep., vol. 125, no. 383, HWS2025-114, pp. 237-242, March 2026.
Paper # HWS2025-114 
Date of Issue 2026-02-25 (VLD, HWS, ICD) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2025-118 HWS2025-114 ICD2025-129

Conference Information
Committee ICD HWS VLD  
Conference Date 2026-03-04 - 2026-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To HWS 
Conference Code 2026-03-ICD-HWS-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Study on Low-Latency Hardware for Post-Quantum Signature QR-UOV 
Sub Title (in English)  
Keyword(1) Post-Quantum Cryptography  
Keyword(2) Digital Signature  
Keyword(3) FPGA  
Keyword(4) QR-UOV  
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1st Author's Name Renma Sugai  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Hiroshi Amagasa  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
3rd Author's Name Rei Ueno  
3rd Author's Affiliation Kyoto University (Kyoto Univ.)
4th Author's Name Naofumi Homma  
4th Author's Affiliation Tohoku University (Tohoku Univ.)
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Speaker Author-1 
Date Time 2026-03-07 11:25:00 
Presentation Time 25 minutes 
Registration for HWS 
Paper # VLD2025-118, HWS2025-114, ICD2025-129 
Volume (vol) vol.125 
Number (no) no.382(VLD), no.383(HWS), no.384(ICD) 
Page pp.237-242 
#Pages 6 
Date of Issue 2026-02-25 (VLD, HWS, ICD) 

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