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Paper Abstract and Keywords
Presentation 2026-08-06 11:15
A Control Point Insertion Method to Increase Gate-Exhaustive Fault Coverage Using UNSAT Cores
Hiroto Kogo, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) CPSY2026-21 DC2026-21 RECONF2026-21
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, as integrated circuits have become increasingly dense and complex, it has been observed that there exist cell-internal defects that cannot be detected by conventional fault models based on signal-line faults. To comprehensively detect such cell-internal defects, the gate-exhaustive fault testing has been proposed. However, this fault model suffers from low fault coverage because re-convergent structures within the circuit frequently give rise to untestable faults. To address this issue, we employ a control-point insertion technique. In this paper, we propose a method that effectively identifies specific locations that cause untestable faults by extracting UNSAT cores derived from those untestable faults, and then inserting control points into the identified locations. Experimental results on ISCAS’89 benchmark circuits demonstrate that inserting control points at only 2% of all signal lines increases the gate-exhaustive fault coverage by 9.46% on average and reduces the number of untestable faults by 67.15% on average.
Keyword (in Japanese) (See Japanese page) 
(in English) gate-exhaustive faults / design for testability / control points / UNSAT core / / / /  
Reference Info. IEICE Tech. Rep., vol. 126, no. 141, DC2026-21, pp. 25-30, Aug. 2026.
Paper # DC2026-21 
Date of Issue 2026-07-30 (CPSY, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2026-21 DC2026-21 RECONF2026-21

Conference Information
Committee CPSY DC RECONF IPSJ-ARC  
Conference Date 2026-08-05 - 2026-08-07 
Place (in Japanese) (See Japanese page) 
Place (in English) Hida Earth Wisdom Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) SWoPP2026: Parallel, Distributed and Cooperative Processing Systems and Dependable Computing 
Paper Information
Registration To DC 
Conference Code 2026-08-CPSY-DC-RECONF-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Control Point Insertion Method to Increase Gate-Exhaustive Fault Coverage Using UNSAT Cores 
Sub Title (in English)  
Keyword(1) gate-exhaustive faults  
Keyword(2) design for testability  
Keyword(3) control points  
Keyword(4) UNSAT core  
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1st Author's Name Hiroto Kogo  
1st Author's Affiliation Nihon University (Nihon Univ)
2nd Author's Name Toshinori Hosokawa  
2nd Author's Affiliation Nihon University (Nihon Univ)
3rd Author's Name Masayoshi Yoshimura  
3rd Author's Affiliation Kyoto Sangyo University (Kyoto Sangyo Univ)
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Speaker Author-1 
Date Time 2026-08-06 11:15:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # CPSY2026-21, DC2026-21, RECONF2026-21 
Volume (vol) vol.126 
Number (no) no.140(CPSY), no.141(DC), no.142(RECONF) 
Page pp.25-30 
#Pages 6 
Date of Issue 2026-07-30 (CPSY, DC, RECONF) 

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