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Technical Committee on Integrated Circuits and Devices (ICD) (Searched in: 2008)
Search Results: Keywords 'from:2008-05-13 to:2008-05-13'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, IPSJ-ARC | 2008-05-13 09:00 |
Tokyo | Branch Target Predictor Utilizing Context Base Value Predictor Tetsurou Hirashima (NRI), Hajime Shimada (Kyoto Univ.), Shinobu Miwa (TUAT), Shinji Tomita (Kyoto Univ.) |
A control dependency is one of the factor which limits instruction level parallelism. To alleviate limitation from the c... [more] | ICD2008-17 pp.1-6 |
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| ICD, IPSJ-ARC | 2008-05-13 09:30 |
Tokyo | Speculation scheme that continues executing mispredicted instructions Takanobu Kita, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai (Univ. of Tokyo) |
Modern processors are acquiring deeper pipelines as their clock frequencies grow higher,leading to large misprediction p... [more] | ICD2008-18 pp.7-12 |
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| ICD, IPSJ-ARC | 2008-05-13 10:00 |
Tokyo | Evaluation of Area-Oriented Register Cache Ryota Shioya (Univ. Tokyo), Hidetsugu Irie (JST), Masahiro Goshima, Shuichi Sakai (Univ. Tokyo) |
Register file is one of the most costly units in recent superscalar processor. In this paper, we evaluate Area-oriented ... [more] | ICD2008-19 pp.13-18 |
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| ICD, IPSJ-ARC | 2008-05-13 10:30 |
Tokyo | An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping Kaito Yamada (Hitachi), Masayoshi Mase, Jun Shirako, Keiji Kimura (Waseda Univ.), Masayuki Ito, Toshihiro Hattori (Renesas), Hiroyuki Mizuno, Kunio Uchiyama (Hitachi), Hironori Kasahara (Waseda Univ.) |
In order to use a large number of processor cores in a chip, hierarchical coarse grain task parallel processing, which e... [more] | ICD2008-20 pp.19-24 |
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| ICD, IPSJ-ARC | 2008-05-13 11:15 |
Tokyo | [Invited Talk]
Multi - Core Processor for Computer System Yoshio Miki (HITACHI)  ICD2008-21 |
In this report, we considered details and the reasons for the multi core processor appearance from the viewpoint of syst... [more] | ICD2008-21 pp.25-28 |
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| ICD, IPSJ-ARC | 2008-05-13 13:45 |
Tokyo | [Invited Talk]
Cell Broadband Engine and SpursEngine as a Muti-core Processor Hiroo Hayashi (Toshiba Corp.) ICD2008-22 |
[more] | ICD2008-22 pp.29-34 |
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| ICD, IPSJ-ARC | 2008-05-13 14:45 |
Tokyo | [Invited Talk]
Intel's vision
-- The Demand for Many Cores: Tera-Scale Usage Models -- Yoshie Munakata (Intel) ICD2008-23 |
[more] | ICD2008-23 pp.35-36 |
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| ICD, IPSJ-ARC | 2008-05-13 16:00 |
Tokyo | [Panel Discussion]
What We Have To Do in Multi-Core Era? Shinji Tomita (Kyoto Univ.), Naoki Nishi (NEC), Mitsuo Saito (Toshiba), Yoshie Munakata (Intel), Aiichiro Inoue (Fujitsu), Toshiyuki Sanuki (IBM Japan), Yasushi Fukunaga (Hitachi) |
[more] | ICD2008-24 pp.37-38 |
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| ICD, IPSJ-ARC | 2008-05-14 09:00 |
Tokyo | A Scalable Multi-core Processor for Mobile Multimedia Applications Hiroyuki Usui, Shuou Nomura, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Jun Tanabe, Masato Uchiyama, Takashi Miyamori, Yoshiro Tsuboi (Toshiba) ICD2008-25 |
We implemented multi-core processor for mobile multimedia applications. Each core consists of 32bit RISC processor and t... [more] | ICD2008-25 pp.39-44 |
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| ICD, IPSJ-ARC | 2008-05-14 09:30 |
Tokyo | Design and Evaluation of a Heterogeneous Multicore SoC with 9 CPUs and 2 Matrix Processors Masami Nakajima, Koichi Ishimi, Naoto Okumura, Norio Masui, Osamu Yamamoto, Hiroyuki Kondo (Renesas) ICD2008-26 |
A multicore SoC has been developed for various applications (recognition, inference, measurement, control and security) ... [more] | ICD2008-26 pp.45-50 |
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| ICD, IPSJ-ARC | 2008-05-14 10:00 |
Tokyo | Multicore Debug Function for Embedded Processor Jun Sakiyama, Makoto Saen (Hitachi, Ltd.), Takehiro Shimizu (Renesas Technology Corp.) |
[more] | ||
| ICD, IPSJ-ARC | 2008-05-14 10:30 |
Tokyo | PSI-SIM: Performance Prediction for Peta-Scale Supercomputers with Thousands of Multi-core Processors Koji Inoue (Kyushu Univ.), Ryutaro Susukita (IST), Hisashige Ando, Shigeru Ishizuki, Hidemi Komatsu (Fujitsu), Yuichi Inadomi, Hiroaki Honda (Kyushu Univ.), Shuji Yamamura (Fujitsu), Hidetomo Shibamura (ISIT), Yunqing Yu, Mutsumi Aoyagi (Kyushu Univ.), Yasunori Kimura (Fujitsu), Kazuaki Murakami (Kyushu Univ.) |
This paper proposes a novel approach to predict the performance of peta-scale supercomputers. It is not easy to accurate... [more] | ICD2008-27 pp.51-56 |
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| ICD, IPSJ-ARC | 2008-05-14 11:15 |
Tokyo | Design of a Multi-Context Field-Programmable VLSI Using Ferroelectric-Based Functional Pass-Gates Noriaki Idobata, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) ICD2008-28 |
Multi-Context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching betw... [more] | ICD2008-28 pp.57-62 |
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| ICD, IPSJ-ARC | 2008-05-14 11:45 |
Tokyo | Architecture of a Stereo Matching VLSI Based on Recursive Computation Keita Tanji, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) ICD2008-29 |
This paper presents a processor architecture for high-speed and reliable trinocular stereo matching based on recursiv... [more] |
ICD2008-29 pp.63-68 |
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| ICD, IPSJ-ARC | 2008-05-14 13:45 |
Tokyo | Automatic Parallelization of Restricted C Programs using Pointer Analysis Masayoshi Mase (Waseda Univ.), Daisuke Baba (Waseda Univ. / Matsushita Electric Industrial), Harumi Nagayama (Waseda Univ. / Intel), Yuta Murata, Keiji Kimura, Hironori Kasahara (Waseda Univ.) |
This paper describes a restriction on pointer usage in C language for parallelism extraction by an automatic parallelizi... [more] | ICD2008-30 pp.69-74 |
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| ICD, IPSJ-ARC | 2008-05-14 14:15 |
Tokyo | Performance Balancing: An Efficient Helper-Thread Execution on CMPs Kenichi Imazato, Naoto Fukumoto, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
Conventional CMPs attempt to exploit the thread-level parallelism (TLP) by using all of the cores integrated in a chip.... [more] |
ICD2008-31 pp.75-80 |
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| ICD, IPSJ-ARC | 2008-05-14 14:45 |
Tokyo | Adaptive Management of Parallelism on Transactional Memories Susumu Takeda, Keita Shimasaki, Koji Inoue, Kazuaki Murakami (kyushu Univ.) |
[more] | ICD2008-32 pp.81-86 |
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| ICD, IPSJ-ARC | 2008-05-14 15:30 |
Tokyo | A Fine Grain Dynamic Sleep Control Scheme in Superscalar Processor Yu Kojima, Daisuke Ikebuchi, Naomi Seki, Yohei Hasegawa, Hideharu Amano (Keio Univ.), Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami (Shibaura Inst of Tech), Tetsuya Sunada, Jun Kanai, Mitaro Namiki (Tokyo Univ. of Agri & Tech), Masaaki Kondo, Hiroshi Nakamura (Univ. of Tokyo) |
Geyser-0 is a low power MIPS R3000 processor which uses a novel fine grain power gating technique to computational units... [more] | ICD2008-33 pp.87-92 |
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| ICD, IPSJ-ARC | 2008-05-14 16:00 |
Tokyo | Considering Performance and Area Overhead in DVS System Utilizing Input Variations Yuji Kunitake (Kyushu U.), Toshinori Sato (Fukuoka U.), Hiroto Yasuura (Kyushu U.) |
The deep submicron semiconductor technologies increase parameter variations and thus the processor design becomes more d... [more] | ICD2008-34 pp.93-98 |
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| ICD, IPSJ-ARC | 2008-05-14 16:30 |
Tokyo | A Low-Latency On-Chip Router Architecture with Prediction Mechanism Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.), Tsutomu Yoshinaga (UEC) |
[more] | ICD2008-35 pp.99-104 |
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