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Technical Committee on VLSI Design Technologies (VLD)  (Searched in: 2008)

Search Results: Keywords 'from:2008-09-29 to:2008-09-29'
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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 13 of 13  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2008-09-29
13:30		 Ishikawa   [Invited Talk] Phase-Adjustable Error Detection Flip-Flops with 2-Stage Hold Driven Optimization and Slack Based Grouping Scheme for Dynamic Voltage Scaling
Masanori Kurimoto, Hiroaki Suzuki (Renesas Technology), Rei Akiyama, Tadao Yamanaka, Haruyuki Okuma (Renesas Design), Hidehiro Takata, Hirofumi Shinohara (Renesas Technology) VLD2008-47		  [more] VLD2008-47
pp.1-6
VLD 2008-09-29
14:45		 Ishikawa   A DFG Mapping Algorithm for Flexible Engine/Generic ALU Array
Masayuki Honma, Ryo Tamura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Makoto Satoh (Hitachi, Ltd.) VLD2008-48		 Reconfigurable processors are processors whose contexts are dynamically reconfigured while they are working. We focus on... [more] VLD2008-48
pp.7-12
VLD 2008-09-29
15:10		 Ishikawa   FFT Design for Flexible Engine/Generic ALU Array and Its Dedicated Synthesis Algorithm
Ryo Tamura, Masayuki Honma, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Makoto Satoh (Hitachi, Ltd.) VLD2008-49		 Reconfigurable processors are those whose contexts are dynamically reconfigured while they are working. We focus on a re... [more] VLD2008-49
pp.13-18
VLD 2008-09-29
15:50		 Ishikawa   Schedulable Resouce Binding under Skew Optimization
Takayuki Obata, Mineo Kaneko (JAIST) VLD2008-50		 In RT-Datapath synthesis, we sometime encounter such problem to find a
control step assignment of control signals (sch... [more]		 VLD2008-50
pp.19-24
VLD 2008-09-29
16:15		 Ishikawa   Delay Variation-Aware Datapath Synthesis Based on Register Clustering
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST) VLD2008-51		 Recently, a novel delay variation-tolerant datapath class named structural robustness against delay variation (SRV) has ... [more] VLD2008-51
pp.25-30
VLD 2008-09-29
16:40		 Ishikawa   Design and Evalution of a Butterfly Circuit Using Selector Logic by Bit-Level Transformation
Takeshi Namura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Motonobu Tonomura (Dai Nippon Print) VLD2008-52		 An arithmetic circuit using selector logic has been proposed,
as a high computational approach for processing.
In thi... [more]		 VLD2008-52
pp.31-36
VLD 2008-09-30
10:00		 Ishikawa   [Invited Talk] On the Order Statistics Applications to EDA, including Non Parametric Statistical Static Timing Analysis
Masanori Imai (STARC/Tokyo Inst. Tech.) VLD2008-53		 Paper presented at DAC2008, titled, ``Non-Parametric Statistical Static Timing Analysis: An SSTA Framework for Arbitrary... [more] VLD2008-53
pp.37-42
VLD 2008-09-30
11:15		 Ishikawa   Overlap-aware Analytical Placement Based on Stable-LSE
Naoto Funatsu, Yasuhiro Takashima (Univ. of Kitakyushu) VLD2008-54		  [more] VLD2008-54
pp.43-48
VLD 2008-09-30
11:40		 Ishikawa   A Routing Method based on Nearest Via Assignment for 2-Layer Ball Grid Array Packages
Yoshiaki Kurata, Yoichi Tomioka, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech) VLD2008-55		  [more] VLD2008-55
pp.49-54
VLD 2008-09-30
13:30		 Ishikawa   Fast configuration experiments of a large-gates optically reconfigurable gate array
Mao Nakajima, Minoru Watanabe (Shizuoka Univ.) VLD2008-56		  [more] VLD2008-56
pp.55-60
VLD 2008-09-30
13:55		 Ishikawa   Fast dynamic optically reconfigurable gate array VLSI
Shinichi Kato, Minoru Watanabe (Shizuoka Univ.) VLD2008-57		  [more] VLD2008-57
pp.61-66
VLD 2008-09-30
14:35		 Ishikawa   A programmable multi-context optical reconfigurable gate array using a PAL-SLM
Shinya Kubota, Minoru Watanabe (Shizuoka Univ.) VLD2008-58		  [more] VLD2008-58
pp.67-70
VLD 2008-09-30
15:00		 Ishikawa   Variable linear transconductance OTA
Masaki Ikemoto, Cong-Kha Pham (UEC) VLD2008-59		 This report propose variable transconductance OTA circuit that have high signal linearity.
The OTA is simulated in a 0.... [more]		 VLD2008-59
pp.71-74
 Results 1 - 13 of 13  /   
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