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Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) (Searched in: 2014)
Search Results: Keywords 'from:2014-05-28 to:2014-05-28'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, IPSJ-SLDM | 2014-05-29 08:30 |
Fukuoka | Kitakyushu International Conference Center | Analog Floorplan with Hierarchical Structure Constraints Shigetoshi Nakatake (Univ. of Kitakyushu)  VLD2014-1 |
[more] | VLD2014-1 pp.1-6 |
| VLD, IPSJ-SLDM | 2014-05-29 08:55 |
Fukuoka | Kitakyushu International Conference Center | Characteristics of Programmable Delay Element based on Channel Decomposition Daijiro Murooka, Koji Nagao, Yu Zhang, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2014-2 |
[more] | VLD2014-2 pp.7-12 |
| VLD, IPSJ-SLDM | 2014-05-29 09:20 |
Fukuoka | Kitakyushu International Conference Center | A Subgradient Method for Analytical Minimization of Half-Perimeter Wirelength Sohta Kayama, Hiroshi Miyashita (Univ. of Kitakyushu) VLD2014-3 |
In this paper, we propose a subgradient method to minimize half-perimeter wire length(HPWL) for circuit placement. Among... [more] | VLD2014-3 pp.13-18 |
| VLD, IPSJ-SLDM | 2014-05-29 09:55 |
Fukuoka | Kitakyushu International Conference Center | [Invited Talk]
Multiple Patterning Lithography by Positive Semidefinite Relaxation Tomomi Matsui (TITECH) VLD2014-4 |
(To be available after the conference date) [more] | VLD2014-4 p.19 |
| VLD, IPSJ-SLDM | 2014-05-29 11:05 |
Fukuoka | Kitakyushu International Conference Center | Proposal of a Synthesis Flow for Asynchronous Circuits with Bundled-Data Implementation from a SystemC Model Taichi Komine, Hiroshi Saito (Univ. of Aizu) VLD2014-5 |
This paper proposes a synthesis flow for asynchronous circuits with bundled-data implementation from a SystemC model to ... [more] | VLD2014-5 pp.21-26 |
| VLD, IPSJ-SLDM | 2014-05-29 11:30 |
Fukuoka | Kitakyushu International Conference Center | LELECUT Triple Patterning Lithography Layout Decomposition using Positive Semidefinite Relaxation Yukihide Kohira (Univ. of Aizu), Tomomi Matsui (Tokyo Tech), Yoko Yokoyama, Chikaaki Kodama (Toshiba), Atsushi Takahashi (Tokyo Tech), Shigeki Nojima, Satoshi Tanaka (Toshiba) VLD2014-6 |
One of the most promising techniques in the 14 nm logic node and beyond is triple patterning lithography (TPL). Recently... [more] | VLD2014-6 pp.27-32 |
| VLD, IPSJ-SLDM | 2014-05-29 13:25 |
Fukuoka | Kitakyushu International Conference Center | Error Tolerance of Dual Pipeline Self Synchronous Circuits Sai Denki, Makoto Ikeda (Univ. of Tokyo) VLD2014-7 |
Soft errors caused by collision of neutrons in cosmic rays and atoms in LSIs in electronic equipment are believed to be ... [more] | VLD2014-7 pp.33-38 |
| VLD, IPSJ-SLDM | 2014-05-29 13:50 |
Fukuoka | Kitakyushu International Conference Center | SOTB 65nm CMOS Design of Gate-Level Dual Pipeline Self-Synchronous Wallace Tree Multiplier Masato Tamura, Makoto Ikeda (Univ. of Tokyo) VLD2014-8 |
Thanks to recent advances, the size of transistor shrinks and degree of integration becomes high. Butbecause of that adv... [more] | VLD2014-8 pp.39-44 |
| VLD, IPSJ-SLDM | 2014-05-29 15:15 |
Fukuoka | Kitakyushu International Conference Center | An Automatic Nested Loop Pipelining Method and Its Evaluation Yusuke Nakatsuji, Masahiro Nambu, Takashi Kambe (Kinki Univ.) VLD2014-9 |
Nested loop pipelining with keeping data dependency is a key transformation in high-level synthesis tools as it helps ma... [more] | VLD2014-9 pp.57-62 |
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