IEICE Technical Committee Submission System
Conference Schedule		 Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

Technical Committee on Dependable Computing (DC)  (Searched in: 2010)

Search Results: Keywords 'from:2010-06-25 to:2010-06-25'
[Go to Official DC Homepage (Japanese)] 
Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2010-06-25
13:30		 Tokyo Kikai-Shinko-Kaikan Bldg. A Full Scan Design Method for Asynchronous Sequential Circuits Based on C-element Scan Paths
Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) DC2010-8		 Using asynchronous VLSI designs resolve synchronous circuit design difficulties, e.g.\ the clock skew, higher throughput... [more] DC2010-8
pp.1-6
DC 2010-06-25
14:00		 Tokyo Kikai-Shinko-Kaikan Bldg. A Class of Partial Thru Testable Sequential Circuits with Multiplexers
Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2010-9		 Partially thru testable sequential circuits are known to be practically testable, and a condition for the testable seque... [more] DC2010-9
pp.7-11
DC 2010-06-25
14:30		 Tokyo Kikai-Shinko-Kaikan Bldg. A Binding Algorithm in High-Level Synthesis for Robust Testable Datapaths
Yuki Yoshikawa, Shun Maruya, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2010-10		  [more] DC2010-10
pp.13-18
DC 2010-06-25
15:15		 Tokyo Kikai-Shinko-Kaikan Bldg. A test pattern matching method on BAST architecture using don't care identification for the detection of random pattern resistant faults
Yun Chen, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) DC2010-11		 BAST is one of techniques which are combined ATPG and BIST to reduce the amount of test data while maintaining the high ... [more] DC2010-11
pp.19-24
DC 2010-06-25
15:45		 Tokyo Kikai-Shinko-Kaikan Bldg. Note on Insertion Point and Area of Observation Circuit for On-Chip Debug Technique
Masayuki Arai, Yoshihiro Tabata, Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2010-12		  [more] DC2010-12
pp.25-30
DC 2010-06-25
16:15		 Tokyo Kikai-Shinko-Kaikan Bldg. An I/O Sequence Slicing Method for Post-silicon Debugging
Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo.) DC2010-13		  [more] DC2010-13
pp.31-36
 Results 1 - 6 of 6  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan