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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2015)
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Search Results: Keywords 'from:2015-05-14 to:2015-05-14'
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[Go to Official VLD Homepage (Japanese)] |
Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Ascending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, IPSJ-SLDM |
2015-05-14 09:15 |
Fukuoka |
Kitakyushu International Conference Center |
A minimum test pattern set generation for large circuits Yusuke Matsunaga (Kyushu Univ.) VLD2015-1 |
[more] |
VLD2015-1 pp.1-6 |
VLD, IPSJ-SLDM |
2015-05-14 09:40 |
Fukuoka |
Kitakyushu International Conference Center |
Use of the subgradient method to minimize half perimeter wirelength with consideration of cell overlap in analytical placement Hiroyuki Iwasaki, Hiroshi Miyashita (The Univ. of Kitakyushu) VLD2015-2 |
Placement continues to be one of the most important tasks in electronic design automation (EDA)
to handle the continua... [more] |
VLD2015-2 pp.7-12 |
VLD, IPSJ-SLDM |
2015-05-14 10:05 |
Fukuoka |
Kitakyushu International Conference Center |
NP-completeness of Routing Problem with Bend Constraint Toshiyuki Hongo, Atsushi Takahashi (Tokyo Tech) VLD2015-3 |
Self-Aligned Quadruple Patterning (SAQP) in which side-wall process is repeated twice is an important manufacturing tech... [more] |
VLD2015-3 pp.13-18 |
VLD, IPSJ-SLDM |
2015-05-14 11:35 |
Fukuoka |
Kitakyushu International Conference Center |
Control Signal Extraction for Sequential Clock Gating Using Time Expansion of Sequential Circuits Tomoya Goto, Kohei Higuchi, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2015-4 |
Recently, clock gating is utilized as a method for reducing the dynamic power of LSI.
Clock gating can be automatically... [more] |
VLD2015-4 pp.31-36 |
VLD, IPSJ-SLDM |
2015-05-14 13:20 |
Fukuoka |
Kitakyushu International Conference Center |
[Invited Talk]
Trends and Future Challenges of Nano-electronics R&D in Japan Seiichiro Kawamura (JST) VLD2015-5 |
(To be available after the conference date) [more] |
VLD2015-5 p.37 |
VLD, IPSJ-SLDM |
2015-05-14 15:00 |
Fukuoka |
Kitakyushu International Conference Center |
Power Analysis Method for a Lightweight Block Cipher Simon Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) VLD2015-6 |
The security of embedded devices such as automotive equipment is very important, because the automobile is connected to ... [more] |
VLD2015-6 pp.45-50 |
VLD, IPSJ-SLDM |
2015-05-14 15:25 |
Fukuoka |
Kitakyushu International Conference Center |
AES Encryption Circuit against Clock Glitch based Fault Analysis Daisuke Hirano, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ) VLD2015-7 |
Recently, fault analysis has attracted a lot of attentions as a new kind of side channel attack methods,in which malicio... [more] |
VLD2015-7 pp.51-55 |
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