Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-17 10:10 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Behavior synthesis to hardware description language NSL of UML activity diagram Toshihiro Kamikage, Ryota Yamazaki, Naohiko Shimizu (Tokai Univ) VLD2010-84 CPSY2010-39 RECONF2010-53 |
In this paper, we will present a set of tools which synthesize the hardware from UML diagrams. In our previous work, We ... [more] |
VLD2010-84 CPSY2010-39 RECONF2010-53 pp.1-6 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-17 10:30 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Implementation and evaluation of program development middleware for Cell Broadband Engine clusters Toshiaki Kamata, Akihiro Shitara, Yuri Nishikawa (Keio Univ.), Masato Yoshimi (Doshisha Univ.), Hideharu Amano (Keio Univ.) VLD2010-85 CPSY2010-40 RECONF2010-54 |
Although accelarators have become prevalent in recent years, it is still difficult to implement many applications on the... [more] |
VLD2010-85 CPSY2010-40 RECONF2010-54 pp.7-12 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-17 11:05 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Proposal and Preliminary Evaluation of System Diagnosis Technique for Large-scale Computer Network by Using Bayesian Network Shingo Harashima (Keio Univ.), Hitoshi Yabusaki (Hitachi.LTD), Wataru Sakamoto (Osaka Univ.), Hiroaki Nishi (Keio Univ.) VLD2010-86 CPSY2010-41 RECONF2010-55 |
For the past network which had comparatively low speed links and simple structure, we could identify the cause of system... [more] |
VLD2010-86 CPSY2010-41 RECONF2010-55 pp.13-18 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-17 11:25 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
implementation of energy management sensor network and application to the home envirnment Yukio Suhara, Tomohisa Nakabe, Hiroaki Nishi (Keio Univ.) VLD2010-87 CPSY2010-42 RECONF2010-56 |
Environmental issues such as global warming and depletion of energy resources are of increasing concern. To prevent the ... [more] |
VLD2010-87 CPSY2010-42 RECONF2010-56 pp.19-24 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-17 11:45 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Highly efficient mapping of electromagnetic wave interactions using the FDTD method for antenna designing on a CUDA-compatible GPU Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Takafumi Fujimoto (Nagasaki Univ.) VLD2010-88 CPSY2010-43 RECONF2010-57 |
This paper describes electromagnetical field simulation using the 3D-FDTD method for antenna designing on a
CUDA-compat... [more] |
VLD2010-88 CPSY2010-43 RECONF2010-57 pp.25-30 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-17 12:05 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Parallelization of the channel width search for FPGA routing Hiroomi Sawada, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto) VLD2010-89 CPSY2010-44 RECONF2010-58 |
As the FPGA becomes resourceful, the design time becomes longer.
Especially, routing process occupies the large portion... [more] |
VLD2010-89 CPSY2010-44 RECONF2010-58 pp.31-36 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-17 13:30 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Approximated Variable Scheduling for High-Level Synthesis Kousuke Sone, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2010-90 CPSY2010-45 RECONF2010-59 |
This article presents approximated variable scheduling methods for high-level synthesis. In the presence of indefinite c... [more] |
VLD2010-90 CPSY2010-45 RECONF2010-59 pp.37-42 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-17 13:50 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
A Heuristic Method using CODCs for Extraction of Maximum Observability Don't Care Set Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) VLD2010-91 CPSY2010-46 RECONF2010-60 |
Sets of observability don't cares (ODCs) can be employed for multi-level logic optimization or propagation analysis of p... [more] |
VLD2010-91 CPSY2010-46 RECONF2010-60 pp.43-48 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-17 14:10 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Power reduction in Dynamically Reconfigurable Processor by Dynamically VDD Switching and a mapping technique to reduce energy overhead Tatsuya Yamamoto (Shibaura Institute), Kazuei Hironaka (Keio Univ.), Yuki Hayakawa (Shibaura Institute), Masayuki Kimura, Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Institute) VLD2010-92 CPSY2010-47 RECONF2010-61 |
This paper describes a dynamic VDD switching technique to reduce energy dissipation of Dynamically Reconfigurable Proces... [more] |
VLD2010-92 CPSY2010-47 RECONF2010-61 pp.49-54 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-17 14:30 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Design and check a ROHM 0.18μm chip with Alliance VHDL toolset
-- Trial the layout and netlist check tools -- Tatsuya Hosokawa, Hiroshi Imai, Naohiko Shimizu (Tokai Univ.) VLD2010-93 CPSY2010-48 RECONF2010-62 |
In this paper, We describe about LSI design with an Alliance CAD tools. An alliance CAD tools is not
enough description... [more] |
VLD2010-93 CPSY2010-48 RECONF2010-62 pp.55-61 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-17 15:05 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Acceleration of Regression Test of Compilers by Program Merging Kazushi Morimoto, Nagisa Ishiura (Kwansei Gakuin Univ.), Yuki Uchiyama (K-OPT), Nobuyuki Hikichi (SRA, Inc) VLD2010-94 CPSY2010-49 RECONF2010-63 |
This article presents a method of accelerating regression test of compilers by merging programs in test suites. Testing ... [more] |
VLD2010-94 CPSY2010-49 RECONF2010-63 pp.63-67 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-17 15:25 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Automatic Retargeting of Binutils and GDB Based on Plug-in Method Soichiro Taga (Kwansei Gakuin Univ.), Takahiro Kumura (NEC/Osaka Univ.), Nagisa Ishiura (Kwansei Gakuin Univ.), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) VLD2010-95 CPSY2010-50 RECONF2010-64 |
This paper proposes a method of automatic retargeting of software development tools based on a plug-in method. The plug-... [more] |
VLD2010-95 CPSY2010-50 RECONF2010-64 pp.69-74 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-17 15:45 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Residue Arithmetic and FIR Filter Design Based on Minimal Signed-Digit Number Representation Rui Chen, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2010-96 CPSY2010-51 RECONF2010-65 |
Residue arithmetic based on a radix-two signed-digit (SD) number system was proposed.Compared to the design of conventio... [more] |
VLD2010-96 CPSY2010-51 RECONF2010-65 pp.75-80 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-17 16:05 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Audio dynamic range compression using polynomial equations Tatsuya Miyashita, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) VLD2010-97 CPSY2010-52 RECONF2010-66 |
An audio signal level compressor is presented, which is based on the approximation algorithm using an interpolating poly... [more] |
VLD2010-97 CPSY2010-52 RECONF2010-66 pp.81-85 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-18 09:00 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
A Regular Expression Matching Circuit Based on Decomposed Automaton Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (KIT) VLD2010-98 CPSY2010-53 RECONF2010-67 |
In this paper, we propose a regular expression matching circuit based on
a decomposed automaton.
To implement regular... [more] |
VLD2010-98 CPSY2010-53 RECONF2010-67 pp.105-110 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-18 09:20 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Encoding Methods of Multiple Data Streams for Hardware Compressors of Floating-Point Data Kentaro Sano, Kazuya Katahira, Satoru Yamamoto (Tohoku Univ.) VLD2010-99 CPSY2010-54 RECONF2010-68 |
[more] |
VLD2010-99 CPSY2010-54 RECONF2010-68 pp.111-116 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-18 09:40 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
FPGA implementation of human detectin with HOG features and AdaBoost Kazuhiro Negi, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) VLD2010-100 CPSY2010-55 RECONF2010-69 |
An increase in in-home accidental deaths of elderly person caused by
falling and fainting, which are nonfatal if detect... [more] |
VLD2010-100 CPSY2010-55 RECONF2010-69 pp.117-122 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-18 10:00 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
A Fundamental Design of a Prototyping Environment to Apply Reconfigurable Logic Devices to Autonomous Recognition and Control Systems Tomonori Izumi (Ritsumeikan Univ.) VLD2010-101 CPSY2010-56 RECONF2010-70 |
Reconfigurable logic devices are expected to be key devices to implement real-time, low-power, small autonomous recognit... [more] |
VLD2010-101 CPSY2010-56 RECONF2010-70 pp.123-126 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-18 10:20 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Evaluation of switchable AES S-box circuit using dynamic and partial reconfiguration Naoko Yamada (Keio Univ.), Keisuke Iwai, Takakazu Kurokawa (NDA), Hideharu Amano (Keio Univ.) VLD2010-102 CPSY2010-57 RECONF2010-71 |
Recently, the threat of side channel attack to the hardware encryption circuits is increasing. In order
to cope with it... [more] |
VLD2010-102 CPSY2010-57 RECONF2010-71 pp.127-132 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-18 10:55 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Feasibility of JHDL for Dynamically Reconfigurable Hardware Design Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ.) VLD2010-103 CPSY2010-58 RECONF2010-72 |
To develop applications for dynamically reconfigurable hardware, the description language which increases the efficienc... [more] |
VLD2010-103 CPSY2010-58 RECONF2010-72 pp.133-138 |