|
|
| Chair |
|
Makoto Ikeda (Univ. of Tokyo) |
| Vice Chair |
|
Toshiyuki Shibuya (Fujitsu Labs.) |
| Secretary |
|
Shigetoshi Nakatake (Univ. of Kitakyushu), Noriyuki Minegishi (Mitsubishi Electric) |
|
| Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) |
[schedule] [select]
|
|
| Chair |
|
Michiaki Muraoka (Kochi Univ.) |
| Secretary |
|
Naoki Iwata (Sony), Koutarou Shimamura (Hitachi), Makoto Sugihara (Kyushu U) |
|
| Conference Date |
Wed, May 28, 2014
Thu, May 29, 2014 08:30 - 16:30 |
| Topics |
System Design, etc. |
| Conference Place |
Kitakyushu International Conference Center |
Contact
Person |
Dr. Makoto Sugihara |
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Thu, May 29 AM
08:30 - 09:45 |
(1)
VLD |
08:30-08:55 |
Analog Floorplan with Hierarchical Structure Constraints  VLD2014-1 |
Shigetoshi Nakatake (Univ. of Kitakyushu) |
(2)
VLD |
08:55-09:20 |
Characteristics of Programmable Delay Element based on Channel Decomposition VLD2014-2 |
Daijiro Murooka, Koji Nagao, Yu Zhang, Shigetoshi Nakatake (Univ. of Kitakyushu) |
(3)
VLD |
09:20-09:45 |
A Subgradient Method for Analytical Minimization of Half-Perimeter Wirelength VLD2014-3 |
Sohta Kayama, Hiroshi Miyashita (Univ. of Kitakyushu) |
| |
09:45-09:55 |
Break ( 10 min. ) |
Thu, May 29 AM
09:55 - 10:55 |
(4)
VLD |
09:55-10:55 |
[Invited Talk]
Multiple Patterning Lithography by Positive Semidefinite Relaxation VLD2014-4 |
Tomomi Matsui (TITECH) |
| |
10:55-11:05 |
Break ( 10 min. ) |
Thu, May 29 AM
11:05 - 11:55 |
(5)
VLD |
11:05-11:30 |
Proposal of a Synthesis Flow for Asynchronous Circuits with Bundled-Data Implementation from a SystemC Model VLD2014-5 |
Taichi Komine, Hiroshi Saito (Univ. of Aizu) |
(6)
VLD |
11:30-11:55 |
LELECUT Triple Patterning Lithography Layout Decomposition using Positive Semidefinite Relaxation VLD2014-6 |
Yukihide Kohira (Univ. of Aizu), Tomomi Matsui (Tokyo Tech), Yoko Yokoyama, Chikaaki Kodama (Toshiba), Atsushi Takahashi (Tokyo Tech), Shigeki Nojima, Satoshi Tanaka (Toshiba) |
| |
11:55-13:25 |
Break ( 90 min. ) |
Thu, May 29 PM
13:25 - 15:05 |
(7)
VLD |
13:25-13:50 |
Error Tolerance of Dual Pipeline Self Synchronous Circuits VLD2014-7 |
Sai Denki, Makoto Ikeda (Univ. of Tokyo) |
(8)
VLD |
13:50-14:15 |
SOTB 65nm CMOS Design of Gate-Level Dual Pipeline Self-Synchronous Wallace Tree Multiplier VLD2014-8 |
Masato Tamura, Makoto Ikeda (Univ. of Tokyo) |
| (9) |
14:15-14:40 |
|
| (10) |
14:40-15:05 |
|
| |
15:05-15:15 |
Break ( 10 min. ) |
Thu, May 29 PM
15:15 - 16:30 |
(11)
VLD |
15:15-15:40 |
An Automatic Nested Loop Pipelining Method and Its Evaluation VLD2014-9 |
Yusuke Nakatsuji, Masahiro Nambu, Takashi Kambe (Kinki Univ.) |
| (12) |
15:40-16:05 |
|
| (13) |
16:05-16:30 |
|
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| VLD |
Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
|
| Contact Address |
Shigetoshi Nakatake (Kitakyushu U)
E- :       k -u |
| Announcement |
See also VLD's homepage:
http://www.ieice.org/~vld/ |
| IPSJ-SLDM |
Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [Latest Schedule]
|
| Contact Address |
Makoto Sugihara (Kyushu U)
Email sldm2013 c aitkshu-u |
| Announcement |
Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/ |
Last modified: 2014-04-16 17:36:10
|