|
|
| Chair |
|
Tomohiro Yoneda (NII) |
| Vice Chair |
|
Seiji Kajihara (Kyushu Inst. of Tech.) |
| Secretary |
|
Masato Kitagami (Chiba Univ.), Tomohiro Nakamura (Hitachi) |
|
| Conference Date |
Fri, Jun 24, 2011 13:00 - 16:50 |
| Topics |
Design, Test, Verification |
| Conference Place |
Room B3-2 Kikai-shinkou-kaikan Building |
| Address |
3-5-8, Shiba-kouen, Ninato-ku, Tokyo 105-0011 Japan |
| Transportation Guide |
http://www.jspmi.or.jp/mapright.htm |
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Notes on Review |
This article is a technical report without peer review, and its polished version will be published elsewhere. |
Fri, Jun 24 PM
13:00 - 14:30 |
| (1) |
13:00-13:30 |
An Approach and Evaluation of Fault Tolerant Sequential Circuits for Simultaneous Occurrence of Multiple Transient Faults  DC2011-8 |
Satoshi Fukumoto, Masayuki Arai, Shinya Hara, Kazuhiko Iwasaki (TMU) |
| (2) |
13:30-14:00 |
Effective multi-cycle signatures in testable response analyzers DC2011-9 |
Yuki Fukazawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
| (3) |
14:00-14:30 |
A study on path selection results of an adaptive field test with process variation and aging degradation for VLSI DC2011-10 |
Satoshi Kashiwazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyuushu Univ) |
| |
14:30-14:40 |
Break ( 10 min. ) |
Fri, Jun 24 PM
14:40 - 15:40 |
| (4) |
14:40-15:40 |
[Invited Talk]
International Conference Report - VTS2011(29th IEEE VLSI Test Symposium) DC2011-11 |
Kazumi Hatayama (NAIST) |
| |
15:40-15:50 |
Break ( 10 min. ) |
Fri, Jun 24 PM
15:50 - 16:50 |
| (5) |
15:50-16:20 |
A don't care identification method with care bit distribution control
-- Application to capture power reduction -- DC2011-12 |
Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ) |
| (6) |
16:20-16:50 |
Low Power At-Speed Scan Testing for LOS Scheme by Test Vector Modification DC2011-13 |
Kohei Miyase, Yuta Uchinodan, Kazunari Enokimoto (KIT), Yuta Yamato (NAIST), Xiaoqing Wen, Seiji Kajihara (KIT), Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Verazel (Lirmm) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 10 minutes for discussion. |
| Invited Talk | Each speech will have 50 minutes for presentation and 10 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| DC |
Technical Committee on Dependable Computing (DC) [Latest Schedule]
|
| Contact Address |
Masato Kitakami
Graduate School of Advanced Integration Science,
Chiba University
1-33 Yayoi-cho Inage-ku, Chiba 263-8522 JAPAN
TEL/FAX +43.290.3039
E- :    f ulty  ba-u |
Last modified: 2011-04-15 23:18:06
|