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| Chair |
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Nobuyasu Kanekawa (Hitachi) |
| Vice Chair |
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Michiko Inoue (NAIST) |
| Secretary |
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Koji Iwata (RTRI), Masayoshi Yoshimura (Kyoto Sangyo Univ.) |
|
| Conference Date |
Wed, Feb 17, 2016 10:00 - 16:30 |
| Topics |
VLSI Design and Test, etc. |
| Conference Place |
|
| Address |
3-5-8, Shiba-Koen, Minato-ku, Tokyo, 105-0111 Japan. |
| Transportation Guide |
http://www.jspmi.or.jp/kaigishitsu/access.html |
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Wed, Feb 17 AM
10:00 - 11:15 |
| (1) |
10:00-10:25 |
Note on Simultaneous Multiple Transient Fault Detection Based on Dual Approximate Logic  DC2015-86 |
Keisuke Sonehara, Masayuki Arai (Nihon Univ.) |
| (2) |
10:25-10:50 |
Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation DC2015-87 |
Fuqiang Li, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara (Kyutech) |
| (3) |
10:50-11:15 |
Reduction of open fault test pattern generation time by selection of adjacent lines for assigning logic value DC2015-88 |
Kazui Fujitnai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) |
| |
11:15-11:30 |
Break ( 15 min. ) |
Wed, Feb 17 AM
11:30 - 12:20 |
| (4) |
11:30-11:55 |
Acceleration of Stochastic Computing by Dynamically Sharing Consecutive Bit Sequences DC2015-89 |
Kensuke Takamori, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) |
| (5) |
11:55-12:20 |
Delay fault injection framework based on logic simulation with zero delay model DC2015-90 |
Shinji Kawasaki, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) |
| |
12:20-14:00 |
Lunch Break ( 100 min. ) |
Wed, Feb 17 PM
14:00 - 15:15 |
| (6) |
14:00-14:25 |
A Ranking Method of Suspicious Candidate Faults Using Fault Excitation Condition Analysis for Universal Logical Fault Diagnosis DC2015-91 |
Hideyuki Takano, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Koji Yamazaki (Meiji Univ.) |
| (7) |
14:25-14:50 |
Built-In Self-Test with Combination of Weighted Random Pattern and Reseeding DC2015-92 |
Sayaka Satonaka, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) |
| (8) |
14:50-15:15 |
An RTL Test Point Insertion Method to Reduce the Number of Test Patterns DC2015-93 |
Naoya Ohsaki, Toshinori Hosokawa, Hiroshi Yamazaki (NU), Masayoshi Yoshimura (KSU) |
| |
- |
Break |
Wed, Feb 17 PM
15:15 - 16:30 |
| (9) |
15:15-15:40 |
Analog Circuit Design for a Precision Resistance Measurement of TSVs DC2015-94 |
Senling Wang, Keisuke Kagawa (Ehime Univ.), Shuichi Kameyama (Fujitsu), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) |
| (10) |
15:40-16:05 |
The Hybrid Communication Protocol for CANs DC2015-95 |
Koji Konomi, Muneyuki Nakamura, Kazuya Sakai, Satoshi Fukumoto (Tokyo Metropolitan Univ.) |
| (11) |
16:05-16:30 |
Study on the Effect of Power Supply Noise on Flip-Flop Circuits DC2015-96 |
Takuya Yamamoto, Yukiya Miura (Tokyo Metropolitan Univ.) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| DC |
Technical Committee on Dependable Computing (DC) [Latest Schedule]
|
| Contact Address |
|
Last modified: 2015-12-23 20:40:52
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